1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A78_H 8*91f16700Schasinglulu #define CORTEX_A78_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define CORTEX_A78_MIDR U(0x410FD410) 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* Cortex-A78 loop count for CVE-2022-23960 mitigation */ 15*91f16700Schasinglulu #define CORTEX_A78_BHB_LOOP_COUNT U(32) 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * CPU Extended Control register specific definitions. 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 21*91f16700Schasinglulu #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 22*91f16700Schasinglulu #define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) 23*91f16700Schasinglulu #define CPUECTLR_EL1_PF_MODE_LSB U(6) 24*91f16700Schasinglulu #define CPUECTLR_EL1_PF_MODE_WIDTH U(2) 25*91f16700Schasinglulu 26*91f16700Schasinglulu /******************************************************************************* 27*91f16700Schasinglulu * CPU Power Control register specific definitions 28*91f16700Schasinglulu ******************************************************************************/ 29*91f16700Schasinglulu #define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 30*91f16700Schasinglulu #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 31*91f16700Schasinglulu 32*91f16700Schasinglulu /******************************************************************************* 33*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 34*91f16700Schasinglulu ******************************************************************************/ 35*91f16700Schasinglulu #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 38*91f16700Schasinglulu #define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0) 39*91f16700Schasinglulu #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) 40*91f16700Schasinglulu #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 41*91f16700Schasinglulu #define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40) 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2 44*91f16700Schasinglulu 45*91f16700Schasinglulu #define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0 46*91f16700Schasinglulu 47*91f16700Schasinglulu /******************************************************************************* 48*91f16700Schasinglulu * CPU Activity Monitor Unit register specific definitions. 49*91f16700Schasinglulu ******************************************************************************/ 50*91f16700Schasinglulu #define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 51*91f16700Schasinglulu #define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 52*91f16700Schasinglulu #define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 53*91f16700Schasinglulu #define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 54*91f16700Schasinglulu 55*91f16700Schasinglulu #define CORTEX_A78_AMU_GROUP0_MASK U(0xF) 56*91f16700Schasinglulu #define CORTEX_A78_AMU_GROUP1_MASK U(0x7) 57*91f16700Schasinglulu 58*91f16700Schasinglulu #endif /* CORTEX_A78_H */ 59