1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A77_H 8*91f16700Schasinglulu #define CORTEX_A77_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A77 MIDR */ 13*91f16700Schasinglulu #define CORTEX_A77_MIDR U(0x410FD0D0) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Cortex-A77 loop count for CVE-2022-23960 mitigation */ 16*91f16700Schasinglulu #define CORTEX_A77_BHB_LOOP_COUNT U(24) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * CPU Extended Control register specific definitions. 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 22*91f16700Schasinglulu #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 23*91f16700Schasinglulu #define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * CPU Power Control register specific definitions. 27*91f16700Schasinglulu ******************************************************************************/ 28*91f16700Schasinglulu #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29*91f16700Schasinglulu #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) 30*91f16700Schasinglulu 31*91f16700Schasinglulu /******************************************************************************* 32*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 33*91f16700Schasinglulu ******************************************************************************/ 34*91f16700Schasinglulu #define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 35*91f16700Schasinglulu #define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 36*91f16700Schasinglulu #define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 39*91f16700Schasinglulu #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 40*91f16700Schasinglulu #define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 41*91f16700Schasinglulu #define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 42*91f16700Schasinglulu #define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 43*91f16700Schasinglulu #define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 44*91f16700Schasinglulu 45*91f16700Schasinglulu #endif /* CORTEX_A77_H */ 46