1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A76AE_H 8*91f16700Schasinglulu #define CORTEX_A76AE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A76AE MIDR for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A76AE_MIDR U(0x410FD0E0) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 16*91f16700Schasinglulu #define CORTEX_A76AE_BHB_LOOP_COUNT U(24) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * CPU Extended Control register specific definitions. 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu #define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */ 24*91f16700Schasinglulu #define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4 27*91f16700Schasinglulu 28*91f16700Schasinglulu #endif /* CORTEX_A76AE_H */ 29