1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A76_H 8*91f16700Schasinglulu #define CORTEX_A76_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A76 MIDR for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A76_MIDR U(0x410fd0b0) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 16*91f16700Schasinglulu #define CORTEX_A76_BHB_LOOP_COUNT U(24) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * CPU Extended Control register specific definitions. 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22*91f16700Schasinglulu #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) 25*91f16700Schasinglulu #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) 26*91f16700Schasinglulu 27*91f16700Schasinglulu /******************************************************************************* 28*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 29*91f16700Schasinglulu ******************************************************************************/ 30*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 31*91f16700Schasinglulu 32*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 39*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 44*91f16700Schasinglulu 45*91f16700Schasinglulu #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 46*91f16700Schasinglulu 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ 49*91f16700Schasinglulu #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) 50*91f16700Schasinglulu 51*91f16700Schasinglulu #endif /* CORTEX_A76_H */ 52