1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A75_H 8*91f16700Schasinglulu #define CORTEX_A75_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A75 MIDR */ 13*91f16700Schasinglulu #define CORTEX_A75_MIDR U(0x410fd0a0) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions. 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19*91f16700Schasinglulu #define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu #define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35) 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ 29*91f16700Schasinglulu #define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4) 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* 34*91f16700Schasinglulu * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are 35*91f16700Schasinglulu * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are 36*91f16700Schasinglulu * programmable by programming the appropriate Event count bits in 37*91f16700Schasinglulu * CPUAMEVTYPER<n> register and are disabled by default. Platforms may 38*91f16700Schasinglulu * enable this with suitable programming. 39*91f16700Schasinglulu */ 40*91f16700Schasinglulu #define CORTEX_A75_AMU_NR_COUNTERS U(5) 41*91f16700Schasinglulu #define CORTEX_A75_AMU_GROUP0_MASK U(0x7) 42*91f16700Schasinglulu #define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) 43*91f16700Schasinglulu 44*91f16700Schasinglulu #ifndef __ASSEMBLER__ 45*91f16700Schasinglulu #include <stdint.h> 46*91f16700Schasinglulu 47*91f16700Schasinglulu uint64_t cortex_a75_amu_cnt_read(int idx); 48*91f16700Schasinglulu void cortex_a75_amu_cnt_write(int idx, uint64_t val); 49*91f16700Schasinglulu unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); 50*91f16700Schasinglulu unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); 51*91f16700Schasinglulu void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); 52*91f16700Schasinglulu void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); 53*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 54*91f16700Schasinglulu 55*91f16700Schasinglulu #endif /* CORTEX_A75_H */ 56