1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A73_H 8*91f16700Schasinglulu #define CORTEX_A73_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A73 midr for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A73_MIDR U(0x410FD090) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions. 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ 19*91f16700Schasinglulu 20*91f16700Schasinglulu #define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6) 21*91f16700Schasinglulu 22*91f16700Schasinglulu /******************************************************************************* 23*91f16700Schasinglulu * L2 Memory Error Syndrome register specific definitions. 24*91f16700Schasinglulu ******************************************************************************/ 25*91f16700Schasinglulu #define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ 26*91f16700Schasinglulu 27*91f16700Schasinglulu /******************************************************************************* 28*91f16700Schasinglulu * CPU implementation defined register specific definitions. 29*91f16700Schasinglulu ******************************************************************************/ 30*91f16700Schasinglulu #define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0 31*91f16700Schasinglulu 32*91f16700Schasinglulu #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 37*91f16700Schasinglulu 38*91f16700Schasinglulu /******************************************************************************* 39*91f16700Schasinglulu * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs 40*91f16700Schasinglulu ******************************************************************************/ 41*91f16700Schasinglulu #ifndef __ASSEMBLER__ 42*91f16700Schasinglulu DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1) 43*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 44*91f16700Schasinglulu 45*91f16700Schasinglulu #endif /* CORTEX_A73_H */ 46