1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A72_H 8*91f16700Schasinglulu #define CORTEX_A72_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A72 midr for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A72_MIDR U(0x410FD080) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Cortex-A72 loop count for CVE-2022-23960 mitigation */ 16*91f16700Schasinglulu #define CORTEX_A72_BHB_LOOP_COUNT U(8) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * CPU Extended Control register specific definitions. 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu #define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 24*91f16700Schasinglulu #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 25*91f16700Schasinglulu #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 26*91f16700Schasinglulu #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 27*91f16700Schasinglulu 28*91f16700Schasinglulu /******************************************************************************* 29*91f16700Schasinglulu * CPU Memory Error Syndrome register specific definitions. 30*91f16700Schasinglulu ******************************************************************************/ 31*91f16700Schasinglulu #define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 32*91f16700Schasinglulu 33*91f16700Schasinglulu /******************************************************************************* 34*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 35*91f16700Schasinglulu ******************************************************************************/ 36*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 39*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 40*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 41*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 42*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 43*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31) 44*91f16700Schasinglulu 45*91f16700Schasinglulu /******************************************************************************* 46*91f16700Schasinglulu * L2 Auxiliary Control register specific definitions. 47*91f16700Schasinglulu ******************************************************************************/ 48*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28) 51*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27) 52*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26) 53*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) 54*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11) 55*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8) 56*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7) 57*91f16700Schasinglulu #define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6) 58*91f16700Schasinglulu 59*91f16700Schasinglulu /******************************************************************************* 60*91f16700Schasinglulu * L2 Control register specific definitions. 61*91f16700Schasinglulu ******************************************************************************/ 62*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 63*91f16700Schasinglulu 64*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) 65*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 68*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) 69*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 70*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9) 71*91f16700Schasinglulu 72*91f16700Schasinglulu #define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) 73*91f16700Schasinglulu #define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) 74*91f16700Schasinglulu #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 75*91f16700Schasinglulu #define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) 76*91f16700Schasinglulu #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) 77*91f16700Schasinglulu #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 78*91f16700Schasinglulu 79*91f16700Schasinglulu /******************************************************************************* 80*91f16700Schasinglulu * L2 Memory Error Syndrome register specific definitions. 81*91f16700Schasinglulu ******************************************************************************/ 82*91f16700Schasinglulu #define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 83*91f16700Schasinglulu 84*91f16700Schasinglulu #endif /* CORTEX_A72_H */ 85