1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A710_H 8*91f16700Schasinglulu #define CORTEX_A710_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define CORTEX_A710_MIDR U(0x410FD470) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A710 loop count for CVE-2022-23960 mitigation */ 13*91f16700Schasinglulu #define CORTEX_A710_BHB_LOOP_COUNT U(32) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 19*91f16700Schasinglulu #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * CPU Power Control register specific definitions 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu #define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25*91f16700Schasinglulu #define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 26*91f16700Schasinglulu 27*91f16700Schasinglulu /******************************************************************************* 28*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 29*91f16700Schasinglulu ******************************************************************************/ 30*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 31*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 32*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 33*91f16700Schasinglulu 34*91f16700Schasinglulu /******************************************************************************* 35*91f16700Schasinglulu * CPU Auxiliary Control register 2 specific definitions. 36*91f16700Schasinglulu ******************************************************************************/ 37*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 38*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 39*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 40*91f16700Schasinglulu 41*91f16700Schasinglulu /******************************************************************************* 42*91f16700Schasinglulu * CPU Auxiliary Control register 5 specific definitions. 43*91f16700Schasinglulu ******************************************************************************/ 44*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 45*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 46*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 47*91f16700Schasinglulu #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 48*91f16700Schasinglulu 49*91f16700Schasinglulu /******************************************************************************* 50*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 51*91f16700Schasinglulu ******************************************************************************/ 52*91f16700Schasinglulu #define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 53*91f16700Schasinglulu #define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 54*91f16700Schasinglulu #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 55*91f16700Schasinglulu #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 56*91f16700Schasinglulu 57*91f16700Schasinglulu /******************************************************************************* 58*91f16700Schasinglulu * CPU Selected Instruction Private register specific definitions. 59*91f16700Schasinglulu ******************************************************************************/ 60*91f16700Schasinglulu #define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0 61*91f16700Schasinglulu #define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1 62*91f16700Schasinglulu #define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 63*91f16700Schasinglulu #define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 64*91f16700Schasinglulu 65*91f16700Schasinglulu #endif /* CORTEX_A710_H */ 66