1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef CORTEX_A57_H 9*91f16700Schasinglulu #define CORTEX_A57_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Cortex-A57 midr for revision 0 */ 14*91f16700Schasinglulu #define CORTEX_A57_MIDR U(0x410FD070) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* Retention timer tick definitions */ 17*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_2 U(0x1) 18*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_8 U(0x2) 19*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_32 U(0x3) 20*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_64 U(0x4) 21*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_128 U(0x5) 22*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_256 U(0x6) 23*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_512 U(0x7) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * CPU Extended Control register specific definitions. 27*91f16700Schasinglulu ******************************************************************************/ 28*91f16700Schasinglulu #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) 31*91f16700Schasinglulu #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 32*91f16700Schasinglulu #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 33*91f16700Schasinglulu #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 36*91f16700Schasinglulu #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 37*91f16700Schasinglulu 38*91f16700Schasinglulu /******************************************************************************* 39*91f16700Schasinglulu * CPU Memory Error Syndrome register specific definitions. 40*91f16700Schasinglulu ******************************************************************************/ 41*91f16700Schasinglulu #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 42*91f16700Schasinglulu 43*91f16700Schasinglulu /******************************************************************************* 44*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 45*91f16700Schasinglulu ******************************************************************************/ 46*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 47*91f16700Schasinglulu 48*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) 49*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58) 50*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 51*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 52*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) 53*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 54*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 55*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) 56*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 57*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) 58*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24) 59*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) 60*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 61*91f16700Schasinglulu 62*91f16700Schasinglulu /******************************************************************************* 63*91f16700Schasinglulu * L2 Control register specific definitions. 64*91f16700Schasinglulu ******************************************************************************/ 65*91f16700Schasinglulu #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 68*91f16700Schasinglulu #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 69*91f16700Schasinglulu 70*91f16700Schasinglulu #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 71*91f16700Schasinglulu #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 72*91f16700Schasinglulu 73*91f16700Schasinglulu #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) 74*91f16700Schasinglulu 75*91f16700Schasinglulu /******************************************************************************* 76*91f16700Schasinglulu * L2 Extended Control register specific definitions. 77*91f16700Schasinglulu ******************************************************************************/ 78*91f16700Schasinglulu #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 79*91f16700Schasinglulu 80*91f16700Schasinglulu #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 81*91f16700Schasinglulu #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 82*91f16700Schasinglulu 83*91f16700Schasinglulu /******************************************************************************* 84*91f16700Schasinglulu * L2 Memory Error Syndrome register specific definitions. 85*91f16700Schasinglulu ******************************************************************************/ 86*91f16700Schasinglulu #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 87*91f16700Schasinglulu 88*91f16700Schasinglulu #endif /* CORTEX_A57_H */ 89