1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A55_H 8*91f16700Schasinglulu #define CORTEX_A55_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A55 MIDR for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A55_MIDR U(0x410fd050) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions. 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19*91f16700Schasinglulu #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) 22*91f16700Schasinglulu 23*91f16700Schasinglulu /******************************************************************************* 24*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu #define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) 29*91f16700Schasinglulu #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) 30*91f16700Schasinglulu #define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) 31*91f16700Schasinglulu 32*91f16700Schasinglulu /******************************************************************************* 33*91f16700Schasinglulu * CPU Identification register specific definitions. 34*91f16700Schasinglulu ******************************************************************************/ 35*91f16700Schasinglulu #define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ 40*91f16700Schasinglulu #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* Instruction patching registers */ 43*91f16700Schasinglulu #define CPUPSELR_EL3 S3_6_C15_C8_0 44*91f16700Schasinglulu #define CPUPCR_EL3 S3_6_C15_C8_1 45*91f16700Schasinglulu #define CPUPOR_EL3 S3_6_C15_C8_2 46*91f16700Schasinglulu #define CPUPMR_EL3 S3_6_C15_C8_3 47*91f16700Schasinglulu 48*91f16700Schasinglulu #endif /* CORTEX_A55_H */ 49