1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A53_H 8*91f16700Schasinglulu #define CORTEX_A53_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A53 midr for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A53_MIDR U(0x410FD030) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Retention timer tick definitions */ 16*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_2 U(0x1) 17*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_8 U(0x2) 18*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_32 U(0x3) 19*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_64 U(0x4) 20*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_128 U(0x5) 21*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_256 U(0x6) 22*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_512 U(0x7) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /******************************************************************************* 25*91f16700Schasinglulu * CPU Extended Control register specific definitions. 26*91f16700Schasinglulu ******************************************************************************/ 27*91f16700Schasinglulu #define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) 32*91f16700Schasinglulu #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) 35*91f16700Schasinglulu #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************************* 38*91f16700Schasinglulu * CPU Memory Error Syndrome register specific definitions. 39*91f16700Schasinglulu ******************************************************************************/ 40*91f16700Schasinglulu #define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) 48*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) 49*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) 50*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) 51*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) 52*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) 53*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) 54*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) 55*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT U(13) 56*91f16700Schasinglulu #define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT) 57*91f16700Schasinglulu 58*91f16700Schasinglulu /******************************************************************************* 59*91f16700Schasinglulu * L2 Auxiliary Control register specific definitions. 60*91f16700Schasinglulu ******************************************************************************/ 61*91f16700Schasinglulu #define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 62*91f16700Schasinglulu 63*91f16700Schasinglulu #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) 64*91f16700Schasinglulu #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) 65*91f16700Schasinglulu /******************************************************************************* 66*91f16700Schasinglulu * L2 Extended Control register specific definitions. 67*91f16700Schasinglulu ******************************************************************************/ 68*91f16700Schasinglulu #define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 69*91f16700Schasinglulu 70*91f16700Schasinglulu #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) 71*91f16700Schasinglulu #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) 72*91f16700Schasinglulu 73*91f16700Schasinglulu /******************************************************************************* 74*91f16700Schasinglulu * L2 Memory Error Syndrome register specific definitions. 75*91f16700Schasinglulu ******************************************************************************/ 76*91f16700Schasinglulu #define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 77*91f16700Schasinglulu 78*91f16700Schasinglulu /******************************************************************************* 79*91f16700Schasinglulu * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs 80*91f16700Schasinglulu ******************************************************************************/ 81*91f16700Schasinglulu #ifndef __ASSEMBLER__ 82*91f16700Schasinglulu DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1) 83*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 84*91f16700Schasinglulu 85*91f16700Schasinglulu #endif /* CORTEX_A53_H */ 86