1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A510_H 8*91f16700Schasinglulu #define CORTEX_A510_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define CORTEX_A510_MIDR U(0x410FD460) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************************* 13*91f16700Schasinglulu * CPU Extended Control register specific definitions 14*91f16700Schasinglulu ******************************************************************************/ 15*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 16*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) 17*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) 18*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) 19*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) 20*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) 21*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) 22*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) 23*91f16700Schasinglulu #define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * CPU Power Control register specific definitions 27*91f16700Schasinglulu ******************************************************************************/ 28*91f16700Schasinglulu #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29*91f16700Schasinglulu #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 30*91f16700Schasinglulu 31*91f16700Schasinglulu /******************************************************************************* 32*91f16700Schasinglulu * Complex auxiliary control register specific definitions 33*91f16700Schasinglulu ******************************************************************************/ 34*91f16700Schasinglulu #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 35*91f16700Schasinglulu #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 36*91f16700Schasinglulu #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) 37*91f16700Schasinglulu #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 38*91f16700Schasinglulu #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) 39*91f16700Schasinglulu #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) 40*91f16700Schasinglulu #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * Auxiliary control register specific definitions 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 46*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) 47*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) 48*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 49*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) 50*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 51*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) 52*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) 53*91f16700Schasinglulu #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) 54*91f16700Schasinglulu 55*91f16700Schasinglulu #endif /* CORTEX_A510_H */ 56