1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A35_H 8*91f16700Schasinglulu #define CORTEX_A35_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A35 Main ID register for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A35_MIDR U(0x410FD040) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions. 17*91f16700Schasinglulu * CPUECTLR_EL1 is an implementation-specific register. 18*91f16700Schasinglulu ******************************************************************************/ 19*91f16700Schasinglulu #define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 20*91f16700Schasinglulu #define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6) 21*91f16700Schasinglulu 22*91f16700Schasinglulu /******************************************************************************* 23*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 24*91f16700Schasinglulu ******************************************************************************/ 25*91f16700Schasinglulu #define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #endif /* CORTEX_A35_H */ 30