1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A9_H 8*91f16700Schasinglulu #define CORTEX_A9_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************************* 13*91f16700Schasinglulu * Cortex-A9 midr with version/revision set to 0 14*91f16700Schasinglulu ******************************************************************************/ 15*91f16700Schasinglulu #define CORTEX_A9_MIDR U(0x410FC090) 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu #define CORTEX_A9_ACTLR_SMP_BIT (U(1) << 6) 21*91f16700Schasinglulu #define CORTEX_A9_ACTLR_FLZW_BIT (U(1) << 3) 22*91f16700Schasinglulu 23*91f16700Schasinglulu /******************************************************************************* 24*91f16700Schasinglulu * CPU Power Control Register 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu #define PCR p15, 0, c15, c0, 0 27*91f16700Schasinglulu 28*91f16700Schasinglulu #ifndef __ASSEMBLER__ 29*91f16700Schasinglulu #include <arch_helpers.h> 30*91f16700Schasinglulu DEFINE_COPROCR_RW_FUNCS(pcr, PCR) 31*91f16700Schasinglulu #endif 32*91f16700Schasinglulu 33*91f16700Schasinglulu #endif /* CORTEX_A9_H */ 34