1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A72_H 8*91f16700Schasinglulu #define CORTEX_A72_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A72 midr for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A72_MIDR U(0x410FD080) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions. 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_A72_ECTLR p15, 1, c15 19*91f16700Schasinglulu 20*91f16700Schasinglulu #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 21*91f16700Schasinglulu #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 22*91f16700Schasinglulu #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 23*91f16700Schasinglulu #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * CPU Memory Error Syndrome register specific definitions. 27*91f16700Schasinglulu ******************************************************************************/ 28*91f16700Schasinglulu #define CORTEX_A72_MERRSR p15, 2, c15 29*91f16700Schasinglulu 30*91f16700Schasinglulu /******************************************************************************* 31*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 32*91f16700Schasinglulu ******************************************************************************/ 33*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR p15, 0, c15 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 36*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) 37*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 38*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) 39*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) 40*91f16700Schasinglulu #define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31) 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * L2 Control register specific definitions. 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) 48*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 51*91f16700Schasinglulu #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 54*91f16700Schasinglulu #define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) 55*91f16700Schasinglulu #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) 56*91f16700Schasinglulu #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 57*91f16700Schasinglulu 58*91f16700Schasinglulu /******************************************************************************* 59*91f16700Schasinglulu * L2 Memory Error Syndrome register specific definitions. 60*91f16700Schasinglulu ******************************************************************************/ 61*91f16700Schasinglulu #define CORTEX_A72_L2MERRSR p15, 3, c15 62*91f16700Schasinglulu 63*91f16700Schasinglulu #endif /* CORTEX_A72_H */ 64