1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A57_H 8*91f16700Schasinglulu #define CORTEX_A57_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-A57 midr for revision 0 */ 13*91f16700Schasinglulu #define CORTEX_A57_MIDR U(0x410FD070) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Retention timer tick definitions */ 16*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_2 U(0x1) 17*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_8 U(0x2) 18*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_32 U(0x3) 19*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_64 U(0x4) 20*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_128 U(0x5) 21*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_256 U(0x6) 22*91f16700Schasinglulu #define RETENTION_ENTRY_TICKS_512 U(0x7) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /******************************************************************************* 25*91f16700Schasinglulu * CPU Extended Control register specific definitions. 26*91f16700Schasinglulu ******************************************************************************/ 27*91f16700Schasinglulu #define CORTEX_A57_ECTLR p15, 1, c15 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) 30*91f16700Schasinglulu #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 31*91f16700Schasinglulu #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 32*91f16700Schasinglulu #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 35*91f16700Schasinglulu #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************************* 38*91f16700Schasinglulu * CPU Memory Error Syndrome register specific definitions. 39*91f16700Schasinglulu ******************************************************************************/ 40*91f16700Schasinglulu #define CORTEX_A57_CPUMERRSR p15, 2, c15 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR p15, 0, c15 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) 48*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58) 49*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) 50*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 51*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) 52*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 53*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) 54*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) 55*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) 56*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27) 57*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25) 58*91f16700Schasinglulu #define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 59*91f16700Schasinglulu 60*91f16700Schasinglulu /******************************************************************************* 61*91f16700Schasinglulu * L2 Control register specific definitions. 62*91f16700Schasinglulu ******************************************************************************/ 63*91f16700Schasinglulu #define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 64*91f16700Schasinglulu 65*91f16700Schasinglulu #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 66*91f16700Schasinglulu #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 67*91f16700Schasinglulu 68*91f16700Schasinglulu #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 69*91f16700Schasinglulu #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 70*91f16700Schasinglulu 71*91f16700Schasinglulu /******************************************************************************* 72*91f16700Schasinglulu * L2 Extended Control register specific definitions. 73*91f16700Schasinglulu ******************************************************************************/ 74*91f16700Schasinglulu #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 75*91f16700Schasinglulu 76*91f16700Schasinglulu #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 77*91f16700Schasinglulu #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 78*91f16700Schasinglulu 79*91f16700Schasinglulu /******************************************************************************* 80*91f16700Schasinglulu * L2 Memory Error Syndrome register specific definitions. 81*91f16700Schasinglulu ******************************************************************************/ 82*91f16700Schasinglulu #define CORTEX_A57_L2MERRSR p15, 3, c15 83*91f16700Schasinglulu 84*91f16700Schasinglulu #endif /* CORTEX_A57_H */ 85