1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A17_H 8*91f16700Schasinglulu #define CORTEX_A17_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************************* 13*91f16700Schasinglulu * Cortex-A17 midr with version/revision set to 0 14*91f16700Schasinglulu ******************************************************************************/ 15*91f16700Schasinglulu #define CORTEX_A17_MIDR U(0x410FC0E0) 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu #define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6) 21*91f16700Schasinglulu 22*91f16700Schasinglulu /******************************************************************************* 23*91f16700Schasinglulu * Implementation defined register specific definitions. 24*91f16700Schasinglulu ******************************************************************************/ 25*91f16700Schasinglulu #define CORTEX_A17_IMP_DEF_REG1 p15, 0, c15, c0, 1 26*91f16700Schasinglulu 27*91f16700Schasinglulu #endif /* CORTEX_A17_H */ 28