1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A15_H 8*91f16700Schasinglulu #define CORTEX_A15_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************************* 13*91f16700Schasinglulu * Auxiliary Control Register 2 specific definitions. 14*91f16700Schasinglulu ******************************************************************************/ 15*91f16700Schasinglulu #define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0) 18*91f16700Schasinglulu 19*91f16700Schasinglulu /******************************************************************************* 20*91f16700Schasinglulu * Cortex-A15 midr with version/revision set to 0 21*91f16700Schasinglulu ******************************************************************************/ 22*91f16700Schasinglulu #define CORTEX_A15_MIDR U(0x410FC0F0) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /******************************************************************************* 25*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 26*91f16700Schasinglulu ******************************************************************************/ 27*91f16700Schasinglulu #define CORTEX_A15_ACTLR_INV_BTB_BIT (U(1) << 0) 28*91f16700Schasinglulu #define CORTEX_A15_ACTLR_SMP_BIT (U(1) << 6) 29*91f16700Schasinglulu 30*91f16700Schasinglulu #endif /* CORTEX_A15_H */ 31