1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: MIT 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * This header provides constants for the ARM GIC. 7*91f16700Schasinglulu */ 8*91f16700Schasinglulu 9*91f16700Schasinglulu #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 10*91f16700Schasinglulu #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <dt-bindings/interrupt-controller/irq.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* interrupt specifier cell 0 */ 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define GIC_SPI 0 17*91f16700Schasinglulu #define GIC_PPI 1 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* 20*91f16700Schasinglulu * Interrupt specifier cell 2. 21*91f16700Schasinglulu * The flags in irq.h are valid, plus those below. 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu #define GIC_CPU_MASK_RAW(x) ((x) << 8) 24*91f16700Schasinglulu #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #endif 27