1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef UART_16550_H 8*91f16700Schasinglulu #define UART_16550_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <drivers/console.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* UART16550 Registers */ 13*91f16700Schasinglulu #define UARTTX 0x0 14*91f16700Schasinglulu #define UARTRX 0x0 15*91f16700Schasinglulu #define UARTDLL 0x0 16*91f16700Schasinglulu #define UARTIER 0x4 17*91f16700Schasinglulu #define UARTDLLM 0x4 18*91f16700Schasinglulu #define UARTIIR 0x8 19*91f16700Schasinglulu #define UARTFCR 0x8 20*91f16700Schasinglulu #define UARTLCR 0xc 21*91f16700Schasinglulu #define UARTMCR 0x10 22*91f16700Schasinglulu #define UARTLSR 0x14 23*91f16700Schasinglulu #define UARTMSR 0x18 24*91f16700Schasinglulu #define UARTSPR 0x1c 25*91f16700Schasinglulu #define UARTCSR 0x20 26*91f16700Schasinglulu /* Some instances have MDR1 defined as well */ 27*91f16700Schasinglulu #define UARTMDR1 0x20 28*91f16700Schasinglulu #define UARTRXFIFOCFG 0x24 29*91f16700Schasinglulu #define UARTMIE 0x28 30*91f16700Schasinglulu #define UARTVNDR 0x2c 31*91f16700Schasinglulu #define UARTASR 0x3c 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* FIFO Control Register bits */ 34*91f16700Schasinglulu #define UARTFCR_FIFOMD_16450 (0 << 6) 35*91f16700Schasinglulu #define UARTFCR_FIFOMD_16550 (1 << 6) 36*91f16700Schasinglulu #define UARTFCR_RXTRIG_1 (0 << 6) 37*91f16700Schasinglulu #define UARTFCR_RXTRIG_4 (1 << 6) 38*91f16700Schasinglulu #define UARTFCR_RXTRIG_8 (2 << 6) 39*91f16700Schasinglulu #define UARTFCR_RXTRIG_16 (3 << 6) 40*91f16700Schasinglulu #define UARTFCR_TXTRIG_1 (0 << 4) 41*91f16700Schasinglulu #define UARTFCR_TXTRIG_4 (1 << 4) 42*91f16700Schasinglulu #define UARTFCR_TXTRIG_8 (2 << 4) 43*91f16700Schasinglulu #define UARTFCR_TXTRIG_16 (3 << 4) 44*91f16700Schasinglulu #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ 45*91f16700Schasinglulu #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ 46*91f16700Schasinglulu #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ 47*91f16700Schasinglulu #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* Line Control Register bits */ 50*91f16700Schasinglulu #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ 51*91f16700Schasinglulu #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ 52*91f16700Schasinglulu #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ 53*91f16700Schasinglulu #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ 54*91f16700Schasinglulu #define UARTLCR_PAR (1 << 3) /* Parity */ 55*91f16700Schasinglulu #define UARTLCR_STOP (1 << 2) /* Stop Bit */ 56*91f16700Schasinglulu #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ 57*91f16700Schasinglulu #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ 58*91f16700Schasinglulu #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ 59*91f16700Schasinglulu #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* Line Status Register bits */ 62*91f16700Schasinglulu #define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ 63*91f16700Schasinglulu #define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ 64*91f16700Schasinglulu #define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ 65*91f16700Schasinglulu #define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ 66*91f16700Schasinglulu #define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ 67*91f16700Schasinglulu #define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ 68*91f16700Schasinglulu #define UARTLSR_FERR (1 << 3) /* Framing Error */ 69*91f16700Schasinglulu #define UARTLSR_PERR (1 << 3) /* Parity Error */ 70*91f16700Schasinglulu #define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ 71*91f16700Schasinglulu #define UARTLSR_RDR_BIT (0) /* Rx Data Ready Bit */ 72*91f16700Schasinglulu #define UARTLSR_RDR (1 << UARTLSR_RDR_BIT) /* Rx Data Ready */ 73*91f16700Schasinglulu 74*91f16700Schasinglulu #ifndef __ASSEMBLER__ 75*91f16700Schasinglulu 76*91f16700Schasinglulu #include <stdint.h> 77*91f16700Schasinglulu 78*91f16700Schasinglulu /* 79*91f16700Schasinglulu * Initialize a new 16550 console instance and register it with the console 80*91f16700Schasinglulu * framework. The |console| pointer must point to storage that will be valid 81*91f16700Schasinglulu * for the lifetime of the console, such as a global or static local variable. 82*91f16700Schasinglulu * Its contents will be reinitialized from scratch. 83*91f16700Schasinglulu * When |clock| has a value of 0, the UART will *not* be initialised. This 84*91f16700Schasinglulu * means the UART should already be enabled and the baudrate and clock setup 85*91f16700Schasinglulu * should have been done already, either by platform specific code or by 86*91f16700Schasinglulu * previous firmware stages. The |baud| parameter will be ignored in this 87*91f16700Schasinglulu * case as well. 88*91f16700Schasinglulu */ 89*91f16700Schasinglulu int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, 90*91f16700Schasinglulu console_t *console); 91*91f16700Schasinglulu 92*91f16700Schasinglulu #endif /*__ASSEMBLER__*/ 93*91f16700Schasinglulu 94*91f16700Schasinglulu #endif /* UART_16550_H */ 95