1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef STM32MP_DDR_H 8*91f16700Schasinglulu #define STM32MP_DDR_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu enum stm32mp_ddr_base_type { 13*91f16700Schasinglulu DDR_BASE, 14*91f16700Schasinglulu DDRPHY_BASE, 15*91f16700Schasinglulu NONE_BASE 16*91f16700Schasinglulu }; 17*91f16700Schasinglulu 18*91f16700Schasinglulu enum stm32mp_ddr_reg_type { 19*91f16700Schasinglulu REG_REG, 20*91f16700Schasinglulu REG_TIMING, 21*91f16700Schasinglulu REG_PERF, 22*91f16700Schasinglulu REG_MAP, 23*91f16700Schasinglulu REGPHY_REG, 24*91f16700Schasinglulu REGPHY_TIMING, 25*91f16700Schasinglulu REG_TYPE_NB 26*91f16700Schasinglulu }; 27*91f16700Schasinglulu 28*91f16700Schasinglulu struct stm32mp_ddr_reg_desc { 29*91f16700Schasinglulu const char *name; 30*91f16700Schasinglulu uint16_t offset; /* Offset for base address */ 31*91f16700Schasinglulu uint8_t par_offset; /* Offset for parameter array */ 32*91f16700Schasinglulu }; 33*91f16700Schasinglulu 34*91f16700Schasinglulu struct stm32mp_ddr_reg_info { 35*91f16700Schasinglulu const char *name; 36*91f16700Schasinglulu const struct stm32mp_ddr_reg_desc *desc; 37*91f16700Schasinglulu uint8_t size; 38*91f16700Schasinglulu enum stm32mp_ddr_base_type base; 39*91f16700Schasinglulu }; 40*91f16700Schasinglulu 41*91f16700Schasinglulu struct stm32mp_ddr_size { 42*91f16700Schasinglulu uint64_t base; 43*91f16700Schasinglulu uint64_t size; 44*91f16700Schasinglulu }; 45*91f16700Schasinglulu 46*91f16700Schasinglulu struct stm32mp_ddr_priv { 47*91f16700Schasinglulu struct stm32mp_ddr_size info; 48*91f16700Schasinglulu struct stm32mp_ddrctl *ctl; 49*91f16700Schasinglulu struct stm32mp_ddrphy *phy; 50*91f16700Schasinglulu uintptr_t pwr; 51*91f16700Schasinglulu uintptr_t rcc; 52*91f16700Schasinglulu }; 53*91f16700Schasinglulu 54*91f16700Schasinglulu struct stm32mp_ddr_info { 55*91f16700Schasinglulu const char *name; 56*91f16700Schasinglulu uint32_t speed; /* in kHz */ 57*91f16700Schasinglulu size_t size; /* Memory size in byte = col * row * width */ 58*91f16700Schasinglulu }; 59*91f16700Schasinglulu 60*91f16700Schasinglulu #define TIMEOUT_US_1S 1000000U 61*91f16700Schasinglulu 62*91f16700Schasinglulu void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type, 63*91f16700Schasinglulu const void *param, const struct stm32mp_ddr_reg_info *ddr_registers); 64*91f16700Schasinglulu void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl); 65*91f16700Schasinglulu void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl); 66*91f16700Schasinglulu void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl); 67*91f16700Schasinglulu int stm32mp_board_ddr_power_init(enum ddr_type ddr_type); 68*91f16700Schasinglulu 69*91f16700Schasinglulu #endif /* STM32MP_DDR_H */ 70