1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef STM32MP1_DDR_H 8*91f16700Schasinglulu #define STM32MP1_DDR_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdbool.h> 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <drivers/st/stm32mp_ddr.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu struct stm32mp1_ddrctrl_reg { 16*91f16700Schasinglulu uint32_t mstr; 17*91f16700Schasinglulu uint32_t mrctrl0; 18*91f16700Schasinglulu uint32_t mrctrl1; 19*91f16700Schasinglulu uint32_t derateen; 20*91f16700Schasinglulu uint32_t derateint; 21*91f16700Schasinglulu uint32_t pwrctl; 22*91f16700Schasinglulu uint32_t pwrtmg; 23*91f16700Schasinglulu uint32_t hwlpctl; 24*91f16700Schasinglulu uint32_t rfshctl0; 25*91f16700Schasinglulu uint32_t rfshctl3; 26*91f16700Schasinglulu uint32_t crcparctl0; 27*91f16700Schasinglulu uint32_t zqctl0; 28*91f16700Schasinglulu uint32_t dfitmg0; 29*91f16700Schasinglulu uint32_t dfitmg1; 30*91f16700Schasinglulu uint32_t dfilpcfg0; 31*91f16700Schasinglulu uint32_t dfiupd0; 32*91f16700Schasinglulu uint32_t dfiupd1; 33*91f16700Schasinglulu uint32_t dfiupd2; 34*91f16700Schasinglulu uint32_t dfiphymstr; 35*91f16700Schasinglulu uint32_t odtmap; 36*91f16700Schasinglulu uint32_t dbg0; 37*91f16700Schasinglulu uint32_t dbg1; 38*91f16700Schasinglulu uint32_t dbgcmd; 39*91f16700Schasinglulu uint32_t poisoncfg; 40*91f16700Schasinglulu uint32_t pccfg; 41*91f16700Schasinglulu }; 42*91f16700Schasinglulu 43*91f16700Schasinglulu struct stm32mp1_ddrctrl_timing { 44*91f16700Schasinglulu uint32_t rfshtmg; 45*91f16700Schasinglulu uint32_t dramtmg0; 46*91f16700Schasinglulu uint32_t dramtmg1; 47*91f16700Schasinglulu uint32_t dramtmg2; 48*91f16700Schasinglulu uint32_t dramtmg3; 49*91f16700Schasinglulu uint32_t dramtmg4; 50*91f16700Schasinglulu uint32_t dramtmg5; 51*91f16700Schasinglulu uint32_t dramtmg6; 52*91f16700Schasinglulu uint32_t dramtmg7; 53*91f16700Schasinglulu uint32_t dramtmg8; 54*91f16700Schasinglulu uint32_t dramtmg14; 55*91f16700Schasinglulu uint32_t odtcfg; 56*91f16700Schasinglulu }; 57*91f16700Schasinglulu 58*91f16700Schasinglulu struct stm32mp1_ddrctrl_map { 59*91f16700Schasinglulu uint32_t addrmap1; 60*91f16700Schasinglulu uint32_t addrmap2; 61*91f16700Schasinglulu uint32_t addrmap3; 62*91f16700Schasinglulu uint32_t addrmap4; 63*91f16700Schasinglulu uint32_t addrmap5; 64*91f16700Schasinglulu uint32_t addrmap6; 65*91f16700Schasinglulu uint32_t addrmap9; 66*91f16700Schasinglulu uint32_t addrmap10; 67*91f16700Schasinglulu uint32_t addrmap11; 68*91f16700Schasinglulu }; 69*91f16700Schasinglulu 70*91f16700Schasinglulu struct stm32mp1_ddrctrl_perf { 71*91f16700Schasinglulu uint32_t sched; 72*91f16700Schasinglulu uint32_t sched1; 73*91f16700Schasinglulu uint32_t perfhpr1; 74*91f16700Schasinglulu uint32_t perflpr1; 75*91f16700Schasinglulu uint32_t perfwr1; 76*91f16700Schasinglulu uint32_t pcfgr_0; 77*91f16700Schasinglulu uint32_t pcfgw_0; 78*91f16700Schasinglulu uint32_t pcfgqos0_0; 79*91f16700Schasinglulu uint32_t pcfgqos1_0; 80*91f16700Schasinglulu uint32_t pcfgwqos0_0; 81*91f16700Schasinglulu uint32_t pcfgwqos1_0; 82*91f16700Schasinglulu #if STM32MP_DDR_DUAL_AXI_PORT 83*91f16700Schasinglulu uint32_t pcfgr_1; 84*91f16700Schasinglulu uint32_t pcfgw_1; 85*91f16700Schasinglulu uint32_t pcfgqos0_1; 86*91f16700Schasinglulu uint32_t pcfgqos1_1; 87*91f16700Schasinglulu uint32_t pcfgwqos0_1; 88*91f16700Schasinglulu uint32_t pcfgwqos1_1; 89*91f16700Schasinglulu #endif 90*91f16700Schasinglulu }; 91*91f16700Schasinglulu 92*91f16700Schasinglulu struct stm32mp1_ddrphy_reg { 93*91f16700Schasinglulu uint32_t pgcr; 94*91f16700Schasinglulu uint32_t aciocr; 95*91f16700Schasinglulu uint32_t dxccr; 96*91f16700Schasinglulu uint32_t dsgcr; 97*91f16700Schasinglulu uint32_t dcr; 98*91f16700Schasinglulu uint32_t odtcr; 99*91f16700Schasinglulu uint32_t zq0cr1; 100*91f16700Schasinglulu uint32_t dx0gcr; 101*91f16700Schasinglulu uint32_t dx1gcr; 102*91f16700Schasinglulu #if STM32MP_DDR_32BIT_INTERFACE 103*91f16700Schasinglulu uint32_t dx2gcr; 104*91f16700Schasinglulu uint32_t dx3gcr; 105*91f16700Schasinglulu #endif 106*91f16700Schasinglulu }; 107*91f16700Schasinglulu 108*91f16700Schasinglulu struct stm32mp1_ddrphy_timing { 109*91f16700Schasinglulu uint32_t ptr0; 110*91f16700Schasinglulu uint32_t ptr1; 111*91f16700Schasinglulu uint32_t ptr2; 112*91f16700Schasinglulu uint32_t dtpr0; 113*91f16700Schasinglulu uint32_t dtpr1; 114*91f16700Schasinglulu uint32_t dtpr2; 115*91f16700Schasinglulu uint32_t mr0; 116*91f16700Schasinglulu uint32_t mr1; 117*91f16700Schasinglulu uint32_t mr2; 118*91f16700Schasinglulu uint32_t mr3; 119*91f16700Schasinglulu }; 120*91f16700Schasinglulu 121*91f16700Schasinglulu struct stm32mp_ddr_config { 122*91f16700Schasinglulu struct stm32mp_ddr_info info; 123*91f16700Schasinglulu struct stm32mp1_ddrctrl_reg c_reg; 124*91f16700Schasinglulu struct stm32mp1_ddrctrl_timing c_timing; 125*91f16700Schasinglulu struct stm32mp1_ddrctrl_map c_map; 126*91f16700Schasinglulu struct stm32mp1_ddrctrl_perf c_perf; 127*91f16700Schasinglulu struct stm32mp1_ddrphy_reg p_reg; 128*91f16700Schasinglulu struct stm32mp1_ddrphy_timing p_timing; 129*91f16700Schasinglulu }; 130*91f16700Schasinglulu 131*91f16700Schasinglulu int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed); 132*91f16700Schasinglulu void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config); 133*91f16700Schasinglulu 134*91f16700Schasinglulu #endif /* STM32MP1_DDR_H */ 135