xref: /arm-trusted-firmware/include/drivers/st/stm32_uart.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef STM32_UART_H
8*91f16700Schasinglulu #define STM32_UART_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu /* UART word length */
11*91f16700Schasinglulu #define STM32_UART_WORDLENGTH_7B		USART_CR1_M1
12*91f16700Schasinglulu #define STM32_UART_WORDLENGTH_8B		0x00000000U
13*91f16700Schasinglulu #define STM32_UART_WORDLENGTH_9B		USART_CR1_M0
14*91f16700Schasinglulu 
15*91f16700Schasinglulu /* UART number of stop bits */
16*91f16700Schasinglulu #define STM32_UART_STOPBITS_0_5			USART_CR2_STOP_0
17*91f16700Schasinglulu #define STM32_UART_STOPBITS_1			0x00000000U
18*91f16700Schasinglulu #define STM32_UART_STOPBITS_1_5			(USART_CR2_STOP_0 | USART_CR2_STOP_1)
19*91f16700Schasinglulu #define STM32_UART_STOPBITS_2			USART_CR2_STOP_1
20*91f16700Schasinglulu 
21*91f16700Schasinglulu /* UART parity */
22*91f16700Schasinglulu #define STM32_UART_PARITY_NONE			0x00000000U
23*91f16700Schasinglulu #define STM32_UART_PARITY_EVEN			USART_CR1_PCE
24*91f16700Schasinglulu #define STM32_UART_PARITY_ODD			(USART_CR1_PCE | USART_CR1_PS)
25*91f16700Schasinglulu 
26*91f16700Schasinglulu /* UART transfer mode */
27*91f16700Schasinglulu #define STM32_UART_MODE_RX			USART_CR1_RE
28*91f16700Schasinglulu #define STM32_UART_MODE_TX			USART_CR1_TE
29*91f16700Schasinglulu #define STM32_UART_MODE_TX_RX			(USART_CR1_TE | USART_CR1_RE)
30*91f16700Schasinglulu 
31*91f16700Schasinglulu /* UART hardware flow control */
32*91f16700Schasinglulu #define STM32_UART_HWCONTROL_NONE		0x00000000U
33*91f16700Schasinglulu #define STM32_UART_HWCONTROL_RTS		USART_CR3_RTSE
34*91f16700Schasinglulu #define STM32_UART_HWCONTROL_CTS		USART_CR3_CTSE
35*91f16700Schasinglulu #define STM32_UART_HWCONTROL_RTS_CTS		(USART_CR3_RTSE | USART_CR3_CTSE)
36*91f16700Schasinglulu 
37*91f16700Schasinglulu /* UART prescaler */
38*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV1		0x00000000U
39*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV2		0x00000001U
40*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV4		0x00000002U
41*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV6		0x00000003U
42*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV8		0x00000004U
43*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV10		0x00000005U
44*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV12		0x00000006U
45*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV16		0x00000007U
46*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV32		0x00000008U
47*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV64		0x00000009U
48*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV128		0x0000000AU
49*91f16700Schasinglulu #define STM32_UART_PRESCALER_DIV256		0x0000000BU
50*91f16700Schasinglulu #define STM32_UART_PRESCALER_NB			0x0000000CU
51*91f16700Schasinglulu 
52*91f16700Schasinglulu /* UART fifo mode */
53*91f16700Schasinglulu #define STM32_UART_FIFOMODE_EN			USART_CR1_FIFOEN
54*91f16700Schasinglulu #define STM32_UART_FIFOMODE_DIS			0x00000000U
55*91f16700Schasinglulu 
56*91f16700Schasinglulu /* UART TXFIFO threshold level */
57*91f16700Schasinglulu #define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL		0x00000000U
58*91f16700Schasinglulu #define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL		USART_CR3_TXFTCFG_0
59*91f16700Schasinglulu #define STM32_UART_TXFIFO_THRESHOLD_HALFFULL		USART_CR3_TXFTCFG_1
60*91f16700Schasinglulu #define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL	(USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1)
61*91f16700Schasinglulu #define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL		USART_CR3_TXFTCFG_2
62*91f16700Schasinglulu #define STM32_UART_TXFIFO_THRESHOLD_EMPTY		(USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0)
63*91f16700Schasinglulu 
64*91f16700Schasinglulu /* UART RXFIFO threshold level */
65*91f16700Schasinglulu #define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL		0x00000000U
66*91f16700Schasinglulu #define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL	USART_CR3_RXFTCFG_0
67*91f16700Schasinglulu #define STM32_UART_RXFIFO_THRESHOLD_HALFFULL		USART_CR3_RXFTCFG_1
68*91f16700Schasinglulu #define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL	(USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1)
69*91f16700Schasinglulu #define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL		USART_CR3_RXFTCFG_2
70*91f16700Schasinglulu #define STM32_UART_RXFIFO_THRESHOLD_FULL		(USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0)
71*91f16700Schasinglulu 
72*91f16700Schasinglulu struct stm32_uart_init_s {
73*91f16700Schasinglulu 	uint32_t baud_rate;		/*
74*91f16700Schasinglulu 					 * Configures the UART communication
75*91f16700Schasinglulu 					 * baud rate.
76*91f16700Schasinglulu 					 */
77*91f16700Schasinglulu 
78*91f16700Schasinglulu 	uint32_t word_length;		/*
79*91f16700Schasinglulu 					 * Specifies the number of data bits
80*91f16700Schasinglulu 					 * transmitted or received in a frame.
81*91f16700Schasinglulu 					 * This parameter can be a value of
82*91f16700Schasinglulu 					 * @ref STM32_UART_WORDLENGTH_*.
83*91f16700Schasinglulu 					 */
84*91f16700Schasinglulu 
85*91f16700Schasinglulu 	uint32_t stop_bits;		/*
86*91f16700Schasinglulu 					 * Specifies the number of stop bits
87*91f16700Schasinglulu 					 * transmitted. This parameter can be
88*91f16700Schasinglulu 					 * a value of @ref STM32_UART_STOPBITS_*.
89*91f16700Schasinglulu 					 */
90*91f16700Schasinglulu 
91*91f16700Schasinglulu 	uint32_t parity;		/*
92*91f16700Schasinglulu 					 * Specifies the parity mode.
93*91f16700Schasinglulu 					 * This parameter can be a value of
94*91f16700Schasinglulu 					 * @ref STM32_UART_PARITY_*.
95*91f16700Schasinglulu 					 */
96*91f16700Schasinglulu 
97*91f16700Schasinglulu 	uint32_t mode;			/*
98*91f16700Schasinglulu 					 * Specifies whether the receive or
99*91f16700Schasinglulu 					 * transmit mode is enabled or
100*91f16700Schasinglulu 					 * disabled. This parameter can be a
101*91f16700Schasinglulu 					 * value of @ref @ref STM32_UART_MODE_*.
102*91f16700Schasinglulu 					 */
103*91f16700Schasinglulu 
104*91f16700Schasinglulu 	uint32_t hw_flow_control;	/*
105*91f16700Schasinglulu 					 * Specifies whether the hardware flow
106*91f16700Schasinglulu 					 * control mode is enabled or
107*91f16700Schasinglulu 					 * disabled. This parameter can be a
108*91f16700Schasinglulu 					 * value of @ref STM32_UARTHWCONTROL_*.
109*91f16700Schasinglulu 					 */
110*91f16700Schasinglulu 
111*91f16700Schasinglulu 	uint32_t one_bit_sampling;	/*
112*91f16700Schasinglulu 					 * Specifies whether a single sample
113*91f16700Schasinglulu 					 * or three samples' majority vote is
114*91f16700Schasinglulu 					 * selected. This parameter can be 0
115*91f16700Schasinglulu 					 * or USART_CR3_ONEBIT.
116*91f16700Schasinglulu 					 */
117*91f16700Schasinglulu 
118*91f16700Schasinglulu 	uint32_t prescaler;		/*
119*91f16700Schasinglulu 					 * Specifies the prescaler value used
120*91f16700Schasinglulu 					 * to divide the UART clock source.
121*91f16700Schasinglulu 					 * This parameter can be a value of
122*91f16700Schasinglulu 					 * @ref STM32_UART_PRESCALER_*.
123*91f16700Schasinglulu 					 */
124*91f16700Schasinglulu 
125*91f16700Schasinglulu 	uint32_t fifo_mode;		/*
126*91f16700Schasinglulu 					 * Specifies if the FIFO mode will be
127*91f16700Schasinglulu 					 * used. This parameter can be a value
128*91f16700Schasinglulu 					 * of @ref STM32_UART_FIFOMODE_*.
129*91f16700Schasinglulu 					 */
130*91f16700Schasinglulu 
131*91f16700Schasinglulu 	uint32_t tx_fifo_threshold;	/*
132*91f16700Schasinglulu 					 * Specifies the TXFIFO threshold
133*91f16700Schasinglulu 					 * level. This parameter can be a
134*91f16700Schasinglulu 					 * value of @ref
135*91f16700Schasinglulu 					 * STM32_UART_TXFIFO_THRESHOLD_*.
136*91f16700Schasinglulu 					 */
137*91f16700Schasinglulu 
138*91f16700Schasinglulu 	uint32_t rx_fifo_threshold;	/*
139*91f16700Schasinglulu 					 * Specifies the RXFIFO threshold
140*91f16700Schasinglulu 					 * level. This parameter can be a
141*91f16700Schasinglulu 					 * value of @ref
142*91f16700Schasinglulu 					 * STM32_UART_RXFIFO_THRESHOLD_*.
143*91f16700Schasinglulu 					 */
144*91f16700Schasinglulu };
145*91f16700Schasinglulu 
146*91f16700Schasinglulu struct stm32_uart_handle_s {
147*91f16700Schasinglulu 	uint32_t base;
148*91f16700Schasinglulu 	uint32_t rdr_mask;
149*91f16700Schasinglulu };
150*91f16700Schasinglulu 
151*91f16700Schasinglulu int stm32_uart_init(struct stm32_uart_handle_s *huart,
152*91f16700Schasinglulu 		    uintptr_t base_addr,
153*91f16700Schasinglulu 		    const struct stm32_uart_init_s *init);
154*91f16700Schasinglulu void stm32_uart_stop(uintptr_t base_addr);
155*91f16700Schasinglulu int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c);
156*91f16700Schasinglulu int stm32_uart_flush(struct stm32_uart_handle_s *huart);
157*91f16700Schasinglulu int stm32_uart_getc(struct stm32_uart_handle_s *huart);
158*91f16700Schasinglulu 
159*91f16700Schasinglulu #endif /* STM32_UART_H */
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