xref: /arm-trusted-firmware/include/drivers/st/stm32_saes.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef STM32_SAES_H
8*91f16700Schasinglulu #define STM32_SAES_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <stdbool.h>
11*91f16700Schasinglulu #include <stddef.h>
12*91f16700Schasinglulu #include <stdint.h>
13*91f16700Schasinglulu 
14*91f16700Schasinglulu #define DT_SAES_COMPAT		"st,stm32-saes"
15*91f16700Schasinglulu 
16*91f16700Schasinglulu struct stm32_saes_platdata {
17*91f16700Schasinglulu 	uintptr_t base;
18*91f16700Schasinglulu 	unsigned long clock_id;
19*91f16700Schasinglulu 	unsigned int reset_id;
20*91f16700Schasinglulu };
21*91f16700Schasinglulu 
22*91f16700Schasinglulu enum stm32_saes_chaining_mode {
23*91f16700Schasinglulu 	STM32_SAES_MODE_ECB,
24*91f16700Schasinglulu 	STM32_SAES_MODE_CBC,
25*91f16700Schasinglulu 	STM32_SAES_MODE_CTR,
26*91f16700Schasinglulu 	STM32_SAES_MODE_GCM,
27*91f16700Schasinglulu 	STM32_SAES_MODE_CCM, /* Not use in TF-A */
28*91f16700Schasinglulu };
29*91f16700Schasinglulu 
30*91f16700Schasinglulu enum stm32_saes_key_selection {
31*91f16700Schasinglulu 	STM32_SAES_KEY_SOFT,
32*91f16700Schasinglulu 	STM32_SAES_KEY_DHU,           /* Derived HW unique key */
33*91f16700Schasinglulu 	STM32_SAES_KEY_BH,            /* Boot HW key */
34*91f16700Schasinglulu 	STM32_SAES_KEY_BHU_XOR_BH,    /* XOR of DHUK and BHK */
35*91f16700Schasinglulu 	STM32_SAES_KEY_WRAPPED
36*91f16700Schasinglulu };
37*91f16700Schasinglulu 
38*91f16700Schasinglulu struct stm32_saes_context {
39*91f16700Schasinglulu 	uintptr_t base;
40*91f16700Schasinglulu 	uint32_t cr;
41*91f16700Schasinglulu 	uint32_t assoc_len;
42*91f16700Schasinglulu 	uint32_t load_len;
43*91f16700Schasinglulu 	uint32_t key[8]; /* In HW byte order */
44*91f16700Schasinglulu 	uint32_t iv[4];  /* In HW byte order */
45*91f16700Schasinglulu };
46*91f16700Schasinglulu 
47*91f16700Schasinglulu int stm32_saes_driver_init(void);
48*91f16700Schasinglulu 
49*91f16700Schasinglulu int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt,
50*91f16700Schasinglulu 		    enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select,
51*91f16700Schasinglulu 		    const void *key, size_t key_len, const void *iv, size_t iv_len);
52*91f16700Schasinglulu int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block,
53*91f16700Schasinglulu 		      uint8_t *data_in, uint8_t *data_out, size_t data_len);
54*91f16700Schasinglulu int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block,
55*91f16700Schasinglulu 			       uint8_t *data, size_t data_len);
56*91f16700Schasinglulu int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block,
57*91f16700Schasinglulu 			   uint8_t *data_in, uint8_t *data_out, size_t data_len);
58*91f16700Schasinglulu int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len);
59*91f16700Schasinglulu #endif
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