1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef DRIVERS_SPI_NOR_H 8*91f16700Schasinglulu #define DRIVERS_SPI_NOR_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <drivers/spi_mem.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* OPCODE */ 13*91f16700Schasinglulu #define SPI_NOR_OP_WREN 0x06U /* Write enable */ 14*91f16700Schasinglulu #define SPI_NOR_OP_WRSR 0x01U /* Write status register 1 byte */ 15*91f16700Schasinglulu #define SPI_NOR_OP_READ_ID 0x9FU /* Read JEDEC ID */ 16*91f16700Schasinglulu #define SPI_NOR_OP_READ_CR 0x35U /* Read configuration register */ 17*91f16700Schasinglulu #define SPI_NOR_OP_READ_SR 0x05U /* Read status register */ 18*91f16700Schasinglulu #define SPI_NOR_OP_READ_FSR 0x70U /* Read flag status register */ 19*91f16700Schasinglulu #define SPINOR_OP_RDEAR 0xC8U /* Read Extended Address Register */ 20*91f16700Schasinglulu #define SPINOR_OP_WREAR 0xC5U /* Write Extended Address Register */ 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* Used for Spansion flashes only. */ 23*91f16700Schasinglulu #define SPINOR_OP_BRWR 0x17U /* Bank register write */ 24*91f16700Schasinglulu #define SPINOR_OP_BRRD 0x16U /* Bank register read */ 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define SPI_NOR_OP_READ 0x03U /* Read data bytes (low frequency) */ 27*91f16700Schasinglulu #define SPI_NOR_OP_READ_FAST 0x0BU /* Read data bytes (high frequency) */ 28*91f16700Schasinglulu #define SPI_NOR_OP_READ_1_1_2 0x3BU /* Read data bytes (Dual Output SPI) */ 29*91f16700Schasinglulu #define SPI_NOR_OP_READ_1_2_2 0xBBU /* Read data bytes (Dual I/O SPI) */ 30*91f16700Schasinglulu #define SPI_NOR_OP_READ_1_1_4 0x6BU /* Read data bytes (Quad Output SPI) */ 31*91f16700Schasinglulu #define SPI_NOR_OP_READ_1_4_4 0xEBU /* Read data bytes (Quad I/O SPI) */ 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* Flags for NOR specific configuration */ 34*91f16700Schasinglulu #define SPI_NOR_USE_FSR BIT(0) 35*91f16700Schasinglulu #define SPI_NOR_USE_BANK BIT(1) 36*91f16700Schasinglulu 37*91f16700Schasinglulu struct nor_device { 38*91f16700Schasinglulu struct spi_mem_op read_op; 39*91f16700Schasinglulu uint32_t size; 40*91f16700Schasinglulu uint32_t flags; 41*91f16700Schasinglulu uint8_t selected_bank; 42*91f16700Schasinglulu uint8_t bank_write_cmd; 43*91f16700Schasinglulu uint8_t bank_read_cmd; 44*91f16700Schasinglulu }; 45*91f16700Schasinglulu 46*91f16700Schasinglulu int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length, 47*91f16700Schasinglulu size_t *length_read); 48*91f16700Schasinglulu int spi_nor_init(unsigned long long *device_size, unsigned int *erase_size); 49*91f16700Schasinglulu 50*91f16700Schasinglulu /* 51*91f16700Schasinglulu * Platform can implement this to override default NOR instance configuration. 52*91f16700Schasinglulu * 53*91f16700Schasinglulu * @device: target NOR instance. 54*91f16700Schasinglulu * Return 0 on success, negative value otherwise. 55*91f16700Schasinglulu */ 56*91f16700Schasinglulu int plat_get_nor_data(struct nor_device *device); 57*91f16700Schasinglulu 58*91f16700Schasinglulu #endif /* DRIVERS_SPI_NOR_H */ 59