1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef DRIVERS_SPI_NAND_H 8*91f16700Schasinglulu #define DRIVERS_SPI_NAND_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <drivers/nand.h> 11*91f16700Schasinglulu #include <drivers/spi_mem.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define SPI_NAND_OP_GET_FEATURE 0x0FU 14*91f16700Schasinglulu #define SPI_NAND_OP_SET_FEATURE 0x1FU 15*91f16700Schasinglulu #define SPI_NAND_OP_READ_ID 0x9FU 16*91f16700Schasinglulu #define SPI_NAND_OP_LOAD_PAGE 0x13U 17*91f16700Schasinglulu #define SPI_NAND_OP_RESET 0xFFU 18*91f16700Schasinglulu #define SPI_NAND_OP_READ_FROM_CACHE 0x03U 19*91f16700Schasinglulu #define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU 20*91f16700Schasinglulu #define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* Configuration register */ 23*91f16700Schasinglulu #define SPI_NAND_REG_CFG 0xB0U 24*91f16700Schasinglulu #define SPI_NAND_CFG_ECC_EN BIT(4) 25*91f16700Schasinglulu #define SPI_NAND_CFG_QE BIT(0) 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* Status register */ 28*91f16700Schasinglulu #define SPI_NAND_REG_STATUS 0xC0U 29*91f16700Schasinglulu #define SPI_NAND_STATUS_BUSY BIT(0) 30*91f16700Schasinglulu #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* Flags for specific configuration */ 33*91f16700Schasinglulu #define SPI_NAND_HAS_QE_BIT BIT(0) 34*91f16700Schasinglulu 35*91f16700Schasinglulu struct spinand_device { 36*91f16700Schasinglulu struct nand_device *nand_dev; 37*91f16700Schasinglulu struct spi_mem_op spi_read_cache_op; 38*91f16700Schasinglulu uint32_t flags; 39*91f16700Schasinglulu uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ 40*91f16700Schasinglulu }; 41*91f16700Schasinglulu 42*91f16700Schasinglulu int spi_nand_init(unsigned long long *size, unsigned int *erase_size); 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* 45*91f16700Schasinglulu * Platform can implement this to override default SPI-NAND instance 46*91f16700Schasinglulu * configuration. 47*91f16700Schasinglulu * 48*91f16700Schasinglulu * @device: target SPI-NAND instance. 49*91f16700Schasinglulu * Return 0 on success, negative value otherwise. 50*91f16700Schasinglulu */ 51*91f16700Schasinglulu int plat_get_spi_nand_data(struct spinand_device *device); 52*91f16700Schasinglulu 53*91f16700Schasinglulu #endif /* DRIVERS_SPI_NAND_H */ 54