1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2) 9*91f16700Schasinglulu #define PLAT_TZC400_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <tzc400.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Structure to configure TZC Regions' boundaries and attributes. */ 14*91f16700Schasinglulu struct tzc400_reg { 15*91f16700Schasinglulu uint8_t reg_filter_en; 16*91f16700Schasinglulu unsigned long long start_addr; 17*91f16700Schasinglulu unsigned long long end_addr; 18*91f16700Schasinglulu unsigned int sec_attr; 19*91f16700Schasinglulu unsigned int nsaid_permissions; 20*91f16700Schasinglulu }; 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define TZC_REGION_NS_NONE 0x00000000U 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* NXP Platforms do not support NS Access ID (NSAID) based non-secure access. 25*91f16700Schasinglulu * Supports only non secure through generic NS ACCESS ID 26*91f16700Schasinglulu */ 27*91f16700Schasinglulu #define TZC_NS_ACCESS_ID 0xFFFFFFFFU 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* Number of DRAM regions to be configured 30*91f16700Schasinglulu * for the platform can be over-written. 31*91f16700Schasinglulu * 32*91f16700Schasinglulu * Array tzc400_reg_list too, needs be over-written 33*91f16700Schasinglulu * if there is any changes to default DRAM region 34*91f16700Schasinglulu * configuration. 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu #ifndef MAX_NUM_TZC_REGION 37*91f16700Schasinglulu /* 3 regions: 38*91f16700Schasinglulu * Region 0(default), 39*91f16700Schasinglulu * Region 1 (DRAM0, Secure Memory), 40*91f16700Schasinglulu * Region 2 (DRAM0, Shared memory) 41*91f16700Schasinglulu */ 42*91f16700Schasinglulu #define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3 43*91f16700Schasinglulu #define DEFAULT_TZASC_CONFIG 1 44*91f16700Schasinglulu #endif 45*91f16700Schasinglulu 46*91f16700Schasinglulu void mem_access_setup(uintptr_t base, uint32_t total_regions, 47*91f16700Schasinglulu struct tzc400_reg *tzc400_reg_list); 48*91f16700Schasinglulu int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list, 49*91f16700Schasinglulu int dram_idx, int list_idx, 50*91f16700Schasinglulu uint64_t dram_start_addr, 51*91f16700Schasinglulu uint64_t dram_size, 52*91f16700Schasinglulu uint32_t secure_dram_sz, 53*91f16700Schasinglulu uint32_t shrd_dram_sz); 54*91f16700Schasinglulu 55*91f16700Schasinglulu #endif /* PLAT_TZC400_H */ 56