1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2018-2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2) 8*91f16700Schasinglulu #define PLAT_TZC380_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <tzc380.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Number of DRAM regions to be configured 13*91f16700Schasinglulu * for the platform can be over-written. 14*91f16700Schasinglulu * 15*91f16700Schasinglulu * Array tzc400_reg_list too, needs be over-written 16*91f16700Schasinglulu * if there is any changes to default DRAM region 17*91f16700Schasinglulu * configuration. 18*91f16700Schasinglulu */ 19*91f16700Schasinglulu #ifndef MAX_NUM_TZC_REGION 20*91f16700Schasinglulu /* 3 regions: 21*91f16700Schasinglulu * Region 0(default), 22*91f16700Schasinglulu * Region 1 (DRAM0, Secure Memory), 23*91f16700Schasinglulu * Region 2 (DRAM0, Shared memory) 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu #define MAX_NUM_TZC_REGION 3 26*91f16700Schasinglulu #define DEFAULT_TZASC_CONFIG 1 27*91f16700Schasinglulu #endif 28*91f16700Schasinglulu 29*91f16700Schasinglulu struct tzc380_reg { 30*91f16700Schasinglulu unsigned int secure; 31*91f16700Schasinglulu unsigned int enabled; 32*91f16700Schasinglulu uint64_t addr; 33*91f16700Schasinglulu uint64_t size; 34*91f16700Schasinglulu unsigned int sub_mask; 35*91f16700Schasinglulu }; 36*91f16700Schasinglulu 37*91f16700Schasinglulu void mem_access_setup(uintptr_t base, uint32_t total_regions, 38*91f16700Schasinglulu struct tzc380_reg *tzc380_reg_list); 39*91f16700Schasinglulu 40*91f16700Schasinglulu int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, 41*91f16700Schasinglulu int dram_idx, int list_idx, 42*91f16700Schasinglulu uint64_t dram_start_addr, 43*91f16700Schasinglulu uint64_t dram_size, 44*91f16700Schasinglulu uint32_t secure_dram_sz, 45*91f16700Schasinglulu uint32_t shrd_dram_sz); 46*91f16700Schasinglulu 47*91f16700Schasinglulu #endif /* PLAT_TZC380_H */ 48