1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu # 9*91f16700Schasinglulu #ifndef NXP_TIMER_H 10*91f16700Schasinglulu #define NXP_TIMER_H 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* System Counter Offset and Bit Mask */ 13*91f16700Schasinglulu #define SYS_COUNTER_CNTCR_OFFSET 0x0 14*91f16700Schasinglulu #define SYS_COUNTER_CNTCR_EN 0x00000001 15*91f16700Schasinglulu #define CNTCR_EN_MASK 0x1 16*91f16700Schasinglulu 17*91f16700Schasinglulu #ifndef __ASSEMBLER__ 18*91f16700Schasinglulu uint64_t get_timer_val(uint64_t start); 19*91f16700Schasinglulu 20*91f16700Schasinglulu #ifdef IMAGE_BL31 21*91f16700Schasinglulu void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base, 22*91f16700Schasinglulu uint8_t ls_config_cntacr, 23*91f16700Schasinglulu uint8_t plat_ls_ns_timer_frame_id); 24*91f16700Schasinglulu void enable_init_timer(void); 25*91f16700Schasinglulu #endif 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* 28*91f16700Schasinglulu * Initialise the nxp on-chip free rolling usec counter as the delay 29*91f16700Schasinglulu * timer. 30*91f16700Schasinglulu */ 31*91f16700Schasinglulu void delay_timer_init(uintptr_t nxp_timer_addr); 32*91f16700Schasinglulu void ls_bl31_timer_init(uintptr_t nxp_timer_addr); 33*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 34*91f16700Schasinglulu 35*91f16700Schasinglulu #endif /* NXP_TIMER_H */ 36