1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2018-2020 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef NXP_SMMU_H 9*91f16700Schasinglulu #define NXP_SMMU_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define SMMU_SCR0 (0x0) 12*91f16700Schasinglulu #define SMMU_NSCR0 (0x400) 13*91f16700Schasinglulu #define SMMU_SACR (0x10) 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define SCR0_CLIENTPD_MASK 0x00000001 16*91f16700Schasinglulu #define SCR0_USFCFG_MASK 0x00000400 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) 19*91f16700Schasinglulu 20*91f16700Schasinglulu static inline void bypass_smmu(uintptr_t smmu_base_addr) 21*91f16700Schasinglulu { 22*91f16700Schasinglulu uint32_t val; 23*91f16700Schasinglulu 24*91f16700Schasinglulu val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) & 25*91f16700Schasinglulu ~(SCR0_USFCFG_MASK); 26*91f16700Schasinglulu mmio_write_32((smmu_base_addr + SMMU_SCR0), val); 27*91f16700Schasinglulu 28*91f16700Schasinglulu val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & 29*91f16700Schasinglulu ~(SCR0_USFCFG_MASK); 30*91f16700Schasinglulu mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu static inline void smmu_cache_unlock(uintptr_t smmu_base_addr) 34*91f16700Schasinglulu { 35*91f16700Schasinglulu uint32_t val; 36*91f16700Schasinglulu 37*91f16700Schasinglulu val = mmio_read_32((smmu_base_addr + SMMU_SACR)); 38*91f16700Schasinglulu val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT; 39*91f16700Schasinglulu mmio_write_32((smmu_base_addr + SMMU_SACR), val); 40*91f16700Schasinglulu } 41*91f16700Schasinglulu 42*91f16700Schasinglulu #endif 43