1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef SFP_H 9*91f16700Schasinglulu #define SFP_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <endian.h> 12*91f16700Schasinglulu #include <lib/mmio.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* SFP Configuration Register Offsets */ 15*91f16700Schasinglulu #define SFP_INGR_OFFSET U(0x20) 16*91f16700Schasinglulu #define SFP_SVHESR_OFFSET U(0x24) 17*91f16700Schasinglulu #define SFP_SFPCR_OFFSET U(0x28) 18*91f16700Schasinglulu #define SFP_VER_OFFSET U(0x38) 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* SFP Hamming register masks for OTPMK and DRV */ 21*91f16700Schasinglulu #define SFP_SVHESR_DRV_MASK U(0x7F) 22*91f16700Schasinglulu #define SFP_SVHESR_OTPMK_MASK U(0x7FC00) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* SFP commands */ 25*91f16700Schasinglulu #define SFP_INGR_READFB_CMD U(0x1) 26*91f16700Schasinglulu #define SFP_INGR_PROGFB_CMD U(0x2) 27*91f16700Schasinglulu #define SFP_INGR_ERROR_MASK U(0x100) 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* SFPCR Masks */ 30*91f16700Schasinglulu #define SFP_SFPCR_WD U(0x80000000) 31*91f16700Schasinglulu #define SFP_SFPCR_WDL U(0x40000000) 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* SFPCR Masks */ 34*91f16700Schasinglulu #define SFP_SFPCR_WD U(0x80000000) 35*91f16700Schasinglulu #define SFP_SFPCR_WDL U(0x40000000) 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define SFP_FUSE_REGS_OFFSET U(0x200) 38*91f16700Schasinglulu 39*91f16700Schasinglulu #ifdef NXP_SFP_VER_3_4 40*91f16700Schasinglulu #define OSPR0_SC_MASK U(0xC000FE35) 41*91f16700Schasinglulu #elif defined(NXP_SFP_VER_3_2) 42*91f16700Schasinglulu #define OSPR0_SC_MASK U(0x0000E035) 43*91f16700Schasinglulu #endif 44*91f16700Schasinglulu 45*91f16700Schasinglulu #if defined(NXP_SFP_VER_3_4) 46*91f16700Schasinglulu #define OSPR_KEY_REVOC_SHIFT U(9) 47*91f16700Schasinglulu #define OSPR_KEY_REVOC_MASK U(0x0000fe00) 48*91f16700Schasinglulu #elif defined(NXP_SFP_VER_3_2) 49*91f16700Schasinglulu #define OSPR_KEY_REVOC_SHIFT U(13) 50*91f16700Schasinglulu #define OSPR_KEY_REVOC_MASK U(0x0000e000) 51*91f16700Schasinglulu #endif /* NXP_SFP_VER_3_4 */ 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define OSPR1_MC_MASK U(0xFFFF0000) 54*91f16700Schasinglulu #define OSPR1_DBG_LVL_MASK U(0x00000007) 55*91f16700Schasinglulu 56*91f16700Schasinglulu #define OSPR_ITS_MASK U(0x00000004) 57*91f16700Schasinglulu #define OSPR_WP_MASK U(0x00000001) 58*91f16700Schasinglulu 59*91f16700Schasinglulu #define MAX_OEM_UID U(5) 60*91f16700Schasinglulu #define SRK_HASH_SIZE U(32) 61*91f16700Schasinglulu 62*91f16700Schasinglulu /* SFP CCSR Register Map */ 63*91f16700Schasinglulu struct sfp_ccsr_regs_t { 64*91f16700Schasinglulu uint32_t ospr; /* 0x200 OSPR0 */ 65*91f16700Schasinglulu uint32_t ospr1; /* 0x204 OSPR1 */ 66*91f16700Schasinglulu uint32_t dcv[2]; /* 0x208 Debug Challenge Value */ 67*91f16700Schasinglulu uint32_t drv[2]; /* 0x210 Debug Response Value */ 68*91f16700Schasinglulu uint32_t fswpr; /* 0x218 FSL Section Write Protect */ 69*91f16700Schasinglulu uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */ 70*91f16700Schasinglulu uint32_t isbcr; /* 0x224 ISBC Configuration */ 71*91f16700Schasinglulu uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */ 72*91f16700Schasinglulu uint32_t otpmk[8]; /* 0x234 OTPMK */ 73*91f16700Schasinglulu uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)]; 74*91f16700Schasinglulu /* 0x254 Super Root Key Hash */ 75*91f16700Schasinglulu uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */ 76*91f16700Schasinglulu }; 77*91f16700Schasinglulu 78*91f16700Schasinglulu uintptr_t get_sfp_addr(void); 79*91f16700Schasinglulu void sfp_init(uintptr_t nxp_sfp_addr); 80*91f16700Schasinglulu uint32_t *get_sfp_srk_hash(void); 81*91f16700Schasinglulu int sfp_check_its(void); 82*91f16700Schasinglulu int sfp_check_oem_wp(void); 83*91f16700Schasinglulu uint32_t get_key_revoc(void); 84*91f16700Schasinglulu void set_sfp_wr_disable(void); 85*91f16700Schasinglulu int sfp_program_fuses(void); 86*91f16700Schasinglulu 87*91f16700Schasinglulu uint32_t sfp_read_oem_uid(uint8_t oem_uid); 88*91f16700Schasinglulu uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val); 89*91f16700Schasinglulu 90*91f16700Schasinglulu #ifdef NXP_SFP_BE 91*91f16700Schasinglulu #define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) 92*91f16700Schasinglulu #define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 93*91f16700Schasinglulu #elif defined(NXP_SFP_LE) 94*91f16700Schasinglulu #define sfp_read32(a) mmio_read_32((uintptr_t)(a)) 95*91f16700Schasinglulu #define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) 96*91f16700Schasinglulu #else 97*91f16700Schasinglulu #error Please define CCSR SFP register endianness 98*91f16700Schasinglulu #endif 99*91f16700Schasinglulu 100*91f16700Schasinglulu #endif/* SFP_H */ 101