1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef SNVS_H 9*91f16700Schasinglulu #define SNVS_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu 12*91f16700Schasinglulu #ifndef __ASSEMBLER__ 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <endian.h> 15*91f16700Schasinglulu #include <stdbool.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu #include <lib/mmio.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu struct snvs_regs { 20*91f16700Schasinglulu uint32_t reserved1; 21*91f16700Schasinglulu uint32_t hp_com; /* 0x04 SNVS_HP Command Register */ 22*91f16700Schasinglulu uint32_t reserved2[3]; 23*91f16700Schasinglulu uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */ 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu 26*91f16700Schasinglulu #ifdef NXP_SNVS_BE 27*91f16700Schasinglulu #define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) 28*91f16700Schasinglulu #define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v))) 29*91f16700Schasinglulu #elif defined(NXP_SNVS_LE) 30*91f16700Schasinglulu #define snvs_read32(a) mmio_read_32((uintptr_t)(a)) 31*91f16700Schasinglulu #define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) 32*91f16700Schasinglulu #else 33*91f16700Schasinglulu #error Please define CCSR SNVS register endianness 34*91f16700Schasinglulu #endif 35*91f16700Schasinglulu 36*91f16700Schasinglulu void snvs_init(uintptr_t nxp_snvs_addr); 37*91f16700Schasinglulu uint32_t get_snvs_state(void); 38*91f16700Schasinglulu void transition_snvs_non_secure(void); 39*91f16700Schasinglulu void transition_snvs_soft_fail(void); 40*91f16700Schasinglulu uint32_t transition_snvs_trusted(void); 41*91f16700Schasinglulu uint32_t transition_snvs_secure(void); 42*91f16700Schasinglulu 43*91f16700Schasinglulu uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos); 44*91f16700Schasinglulu void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val); 45*91f16700Schasinglulu 46*91f16700Schasinglulu void snvs_disable_zeroize_lp_gpr(void); 47*91f16700Schasinglulu 48*91f16700Schasinglulu #if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB) 49*91f16700Schasinglulu uint32_t snvs_read_app_data(void); 50*91f16700Schasinglulu uint32_t snvs_read_app_data_bit(uint32_t bit_pos); 51*91f16700Schasinglulu void snvs_clear_app_data(void); 52*91f16700Schasinglulu void snvs_write_app_data_bit(uint32_t bit_pos); 53*91f16700Schasinglulu #endif 54*91f16700Schasinglulu 55*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 56*91f16700Schasinglulu 57*91f16700Schasinglulu /* SSM_ST field in SNVS status reg */ 58*91f16700Schasinglulu #define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */ 59*91f16700Schasinglulu #define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */ 60*91f16700Schasinglulu #define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */ 61*91f16700Schasinglulu #define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */ 62*91f16700Schasinglulu #define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */ 63*91f16700Schasinglulu #define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */ 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* SNVS register bits */ 66*91f16700Schasinglulu #define HPCOM_SW_SV 0x100 /* Security Violation bit */ 67*91f16700Schasinglulu #define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */ 68*91f16700Schasinglulu #define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */ 69*91f16700Schasinglulu #define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ 70*91f16700Schasinglulu #define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ 71*91f16700Schasinglulu 72*91f16700Schasinglulu #define NXP_LP_GPR0_OFFSET 0x90 73*91f16700Schasinglulu #define NXP_LPCR_OFFSET 0x38 74*91f16700Schasinglulu #define NXP_GPR_Z_DIS_BIT 24 75*91f16700Schasinglulu 76*91f16700Schasinglulu #ifdef NXP_COINED_BB 77*91f16700Schasinglulu 78*91f16700Schasinglulu #ifndef NXP_APP_DATA_LP_GPR_OFFSET 79*91f16700Schasinglulu #define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET 80*91f16700Schasinglulu #endif 81*91f16700Schasinglulu 82*91f16700Schasinglulu #define NXP_LPGPR_ZEROTH_BIT 0 83*91f16700Schasinglulu 84*91f16700Schasinglulu #endif /* NXP_COINED_BB */ 85*91f16700Schasinglulu 86*91f16700Schasinglulu #endif /* SNVS_H */ 87