1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef QSPI_H 9*91f16700Schasinglulu #define QSPI_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <endian.h> 12*91f16700Schasinglulu #include <lib/mmio.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define CHS_QSPI_MCR 0x01550000 15*91f16700Schasinglulu #define CHS_QSPI_64LE 0xC 16*91f16700Schasinglulu 17*91f16700Schasinglulu #ifdef NXP_QSPI_BE 18*91f16700Schasinglulu #define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 19*91f16700Schasinglulu #define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 20*91f16700Schasinglulu #elif defined(NXP_QSPI_LE) 21*91f16700Schasinglulu #define qspi_in32(a) mmio_read_32((uintptr_t)(a)) 22*91f16700Schasinglulu #define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) 23*91f16700Schasinglulu #else 24*91f16700Schasinglulu #error Please define CCSR QSPI register endianness 25*91f16700Schasinglulu #endif 26*91f16700Schasinglulu 27*91f16700Schasinglulu int qspi_io_setup(uintptr_t nxp_qspi_flash_addr, 28*91f16700Schasinglulu size_t nxp_qspi_flash_size, 29*91f16700Schasinglulu uintptr_t fip_offset); 30*91f16700Schasinglulu #endif /* __QSPI_H__ */ 31