1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PMU_H 9*91f16700Schasinglulu #define PMU_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu /* PMU Registers' OFFSET */ 12*91f16700Schasinglulu #define PMU_PCPW20SR_OFFSET 0x830 13*91f16700Schasinglulu #define PMU_CLL2FLUSHSETR_OFFSET 0x1110 14*91f16700Schasinglulu #define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114 15*91f16700Schasinglulu #define PMU_CLL2FLUSHSR_OFFSET 0x1118 16*91f16700Schasinglulu #define PMU_POWMGTCSR_VAL (1 << 20) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* PMU Registers */ 19*91f16700Schasinglulu #define CORE_TIMEBASE_ENBL_OFFSET 0x8A0 20*91f16700Schasinglulu #define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define PMU_IDLE_CLUSTER_MASK 0x2 23*91f16700Schasinglulu #define PMU_FLUSH_CLUSTER_MASK 0x2 24*91f16700Schasinglulu #define PMU_IDLE_CORE_MASK 0xfe 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* pmu register offsets and bitmaps */ 27*91f16700Schasinglulu #define PMU_POWMGTDCR0_OFFSET 0xC20 28*91f16700Schasinglulu #define PMU_POWMGTCSR_OFFSET 0x4000 29*91f16700Schasinglulu #define PMU_CLAINACTSETR_OFFSET 0x1100 30*91f16700Schasinglulu #define PMU_CLAINACTCLRR_OFFSET 0x1104 31*91f16700Schasinglulu #define PMU_CLSINACTSETR_OFFSET 0x1108 32*91f16700Schasinglulu #define PMU_CLSINACTCLRR_OFFSET 0x110C 33*91f16700Schasinglulu #define PMU_CLL2FLUSHSETR_OFFSET 0x1110 34*91f16700Schasinglulu #define PMU_CLL2FLUSHCLRR_OFFSET 0x1114 35*91f16700Schasinglulu #define PMU_IPPDEXPCR0_OFFSET 0x4040 36*91f16700Schasinglulu #define PMU_IPPDEXPCR1_OFFSET 0x4044 37*91f16700Schasinglulu #define PMU_IPPDEXPCR2_OFFSET 0x4048 38*91f16700Schasinglulu #define PMU_IPPDEXPCR3_OFFSET 0x404C 39*91f16700Schasinglulu #define PMU_IPPDEXPCR4_OFFSET 0x4050 40*91f16700Schasinglulu #define PMU_IPPDEXPCR5_OFFSET 0x4054 41*91f16700Schasinglulu #define PMU_IPPDEXPCR6_OFFSET 0x4058 42*91f16700Schasinglulu #define PMU_IPSTPCR0_OFFSET 0x4120 43*91f16700Schasinglulu #define PMU_IPSTPCR1_OFFSET 0x4124 44*91f16700Schasinglulu #define PMU_IPSTPCR2_OFFSET 0x4128 45*91f16700Schasinglulu #define PMU_IPSTPCR3_OFFSET 0x412C 46*91f16700Schasinglulu #define PMU_IPSTPCR4_OFFSET 0x4130 47*91f16700Schasinglulu #define PMU_IPSTPCR5_OFFSET 0x4134 48*91f16700Schasinglulu #define PMU_IPSTPCR6_OFFSET 0x4138 49*91f16700Schasinglulu #define PMU_IPSTPACKSR0_OFFSET 0x4140 50*91f16700Schasinglulu #define PMU_IPSTPACKSR1_OFFSET 0x4144 51*91f16700Schasinglulu #define PMU_IPSTPACKSR2_OFFSET 0x4148 52*91f16700Schasinglulu #define PMU_IPSTPACKSR3_OFFSET 0x414C 53*91f16700Schasinglulu #define PMU_IPSTPACKSR4_OFFSET 0x4150 54*91f16700Schasinglulu #define PMU_IPSTPACKSR5_OFFSET 0x4154 55*91f16700Schasinglulu #define PMU_IPSTPACKSR6_OFFSET 0x4158 56*91f16700Schasinglulu 57*91f16700Schasinglulu #define CLAINACT_DISABLE_ACP 0xFF 58*91f16700Schasinglulu #define CLSINACT_DISABLE_SKY 0xFF 59*91f16700Schasinglulu #define POWMGTDCR_STP_OV_EN 0x1 60*91f16700Schasinglulu #define POWMGTCSR_LPM20_REQ 0x00100000 61*91f16700Schasinglulu 62*91f16700Schasinglulu /* Used by PMU */ 63*91f16700Schasinglulu #define DEVDISR1_MASK 0x024F3504 64*91f16700Schasinglulu #define DEVDISR2_MASK 0x0003FFFF 65*91f16700Schasinglulu #define DEVDISR3_MASK 0x0000303F 66*91f16700Schasinglulu #define DEVDISR4_MASK 0x0000FFFF 67*91f16700Schasinglulu #define DEVDISR5_MASK 0x00F07603 68*91f16700Schasinglulu #define DEVDISR6_MASK 0x00000001 69*91f16700Schasinglulu 70*91f16700Schasinglulu #ifndef __ASSEMBLER__ 71*91f16700Schasinglulu void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr); 72*91f16700Schasinglulu void enable_core_tb(uintptr_t nxp_pmu_addr); 73*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 74*91f16700Schasinglulu 75*91f16700Schasinglulu #endif 76