1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef IFC_NAND_H 8*91f16700Schasinglulu #define IFC_NAND_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */ 11*91f16700Schasinglulu 12*91f16700Schasinglulu int ifc_nand_init(uintptr_t *block_dev_spec, 13*91f16700Schasinglulu uintptr_t ifc_region_addr, 14*91f16700Schasinglulu uintptr_t ifc_register_addr, 15*91f16700Schasinglulu size_t ifc_sram_size, 16*91f16700Schasinglulu uintptr_t ifc_nand_blk_offset, 17*91f16700Schasinglulu size_t ifc_nand_blk_size); 18*91f16700Schasinglulu 19*91f16700Schasinglulu #endif /*IFC_NAND_H*/ 20