1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PLAT_GICV2_H 9*91f16700Schasinglulu #define PLAT_GICV2_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <drivers/arm/gicv2.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* register offsets */ 14*91f16700Schasinglulu #define GICD_CTLR_OFFSET 0x0 15*91f16700Schasinglulu #define GICD_CPENDSGIR3_OFFSET 0xF1C 16*91f16700Schasinglulu #define GICD_SPENDSGIR3_OFFSET 0xF2C 17*91f16700Schasinglulu #define GICD_SGIR_OFFSET 0xF00 18*91f16700Schasinglulu #define GICD_IGROUPR0_OFFSET 0x080 19*91f16700Schasinglulu #define GICD_TYPER_OFFSET 0x0004 20*91f16700Schasinglulu #define GICD_ISENABLER0_OFFSET 0x0100 21*91f16700Schasinglulu #define GICD_ICENABLER0_OFFSET 0x0180 22*91f16700Schasinglulu #define GICD_IPRIORITYR3_OFFSET 0x040C 23*91f16700Schasinglulu #define GICD_ISENABLERn_OFFSET 0x0100 24*91f16700Schasinglulu #define GICD_ISACTIVER0_OFFSET 0x300 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define GICC_CTLR_OFFSET 0x0 27*91f16700Schasinglulu #define GICC_PMR_OFFSET 0x0004 28*91f16700Schasinglulu #define GICC_IAR_OFFSET 0x000C 29*91f16700Schasinglulu #define GICC_DIR_OFFSET 0x1000 30*91f16700Schasinglulu #define GICC_EOIR_OFFSET 0x0010 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* bitfield masks */ 33*91f16700Schasinglulu #define GICC_CTLR_EN_GRP0 0x1 34*91f16700Schasinglulu #define GICC_CTLR_EN_GRP1 0x2 35*91f16700Schasinglulu #define GICC_CTLR_EOImodeS_MASK 0x200 36*91f16700Schasinglulu #define GICC_CTLR_DIS_BYPASS 0x60 37*91f16700Schasinglulu #define GICC_CTLR_CBPR_MASK 0x10 38*91f16700Schasinglulu #define GICC_CTLR_FIQ_EN_MASK 0x8 39*91f16700Schasinglulu #define GICC_CTLR_ACKCTL_MASK 0x4 40*91f16700Schasinglulu #define GICC_PMR_FILTER 0xFF 41*91f16700Schasinglulu 42*91f16700Schasinglulu #define GICD_CTLR_EN_GRP0 0x1 43*91f16700Schasinglulu #define GICD_CTLR_EN_GRP1 0x2 44*91f16700Schasinglulu #define GICD_IGROUP0_SGI15 0x8000 45*91f16700Schasinglulu #define GICD_ISENABLE0_SGI15 0x8000 46*91f16700Schasinglulu #define GICD_ICENABLE0_SGI15 0x8000 47*91f16700Schasinglulu #define GICD_ISACTIVER0_SGI15 0x8000 48*91f16700Schasinglulu #define GICD_CPENDSGIR_CLR_MASK 0xFF000000 49*91f16700Schasinglulu #define GICD_IPRIORITY_SGI15_MASK 0xFF000000 50*91f16700Schasinglulu #define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000 51*91f16700Schasinglulu #define GICD_SPENDSGIR3_SGI15_OFFSET 0x18 52*91f16700Schasinglulu 53*91f16700Schasinglulu #ifndef __ASSEMBLER__ 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* GIC common API's */ 56*91f16700Schasinglulu void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr, 57*91f16700Schasinglulu const uintptr_t nxp_gicc_addr, 58*91f16700Schasinglulu uint8_t plat_core_count, 59*91f16700Schasinglulu interrupt_prop_t *ls_interrupt_props, 60*91f16700Schasinglulu uint8_t ls_interrupt_prop_count, 61*91f16700Schasinglulu uint32_t *target_mask_array); 62*91f16700Schasinglulu void plat_ls_gic_init(void); 63*91f16700Schasinglulu void plat_ls_gic_cpuif_enable(void); 64*91f16700Schasinglulu void plat_ls_gic_cpuif_disable(void); 65*91f16700Schasinglulu void plat_ls_gic_redistif_on(void); 66*91f16700Schasinglulu void plat_ls_gic_redistif_off(void); 67*91f16700Schasinglulu void plat_gic_pcpu_init(void); 68*91f16700Schasinglulu /* GIC utility functions */ 69*91f16700Schasinglulu void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base); 70*91f16700Schasinglulu #endif 71*91f16700Schasinglulu 72*91f16700Schasinglulu #endif /* PLAT_GICV2_H */ 73