1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef DDR_OPTS_H 9*91f16700Schasinglulu #define DDR_OPTS_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */ 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define DDR_BC4 4 /* burst chop */ 14*91f16700Schasinglulu #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 15*91f16700Schasinglulu #define DDR_BL8 8 /* burst length 8 */ 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define DDR4_RTT_OFF 0 18*91f16700Schasinglulu #define DDR4_RTT_60_OHM 1 /* RZQ/4 */ 19*91f16700Schasinglulu #define DDR4_RTT_120_OHM 2 /* RZQ/2 */ 20*91f16700Schasinglulu #define DDR4_RTT_40_OHM 3 /* RZQ/6 */ 21*91f16700Schasinglulu #define DDR4_RTT_240_OHM 4 /* RZQ/1 */ 22*91f16700Schasinglulu #define DDR4_RTT_48_OHM 5 /* RZQ/5 */ 23*91f16700Schasinglulu #define DDR4_RTT_80_OHM 6 /* RZQ/3 */ 24*91f16700Schasinglulu #define DDR4_RTT_34_OHM 7 /* RZQ/7 */ 25*91f16700Schasinglulu #define DDR4_RTT_WR_OFF 0 26*91f16700Schasinglulu #define DDR4_RTT_WR_120_OHM 1 27*91f16700Schasinglulu #define DDR4_RTT_WR_240_OHM 2 28*91f16700Schasinglulu #define DDR4_RTT_WR_HZ 3 29*91f16700Schasinglulu #define DDR4_RTT_WR_80_OHM 4 30*91f16700Schasinglulu #define DDR_ODT_NEVER 0x0 31*91f16700Schasinglulu #define DDR_ODT_CS 0x1 32*91f16700Schasinglulu #define DDR_ODT_ALL_OTHER_CS 0x2 33*91f16700Schasinglulu #define DDR_ODT_OTHER_DIMM 0x3 34*91f16700Schasinglulu #define DDR_ODT_ALL 0x4 35*91f16700Schasinglulu #define DDR_ODT_SAME_DIMM 0x5 36*91f16700Schasinglulu #define DDR_ODT_CS_AND_OTHER_DIMM 0x6 37*91f16700Schasinglulu #define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 38*91f16700Schasinglulu #define DDR_BA_INTLV_CS01 0x40 39*91f16700Schasinglulu #define DDR_BA_INTLV_CS0123 0x64 40*91f16700Schasinglulu #define DDR_BA_NONE 0 41*91f16700Schasinglulu #define DDR_256B_INTLV 0x8 42*91f16700Schasinglulu 43*91f16700Schasinglulu struct memctl_opt { 44*91f16700Schasinglulu int rdimm; 45*91f16700Schasinglulu unsigned int dbw_cap_shift; 46*91f16700Schasinglulu struct local_opts_s { 47*91f16700Schasinglulu unsigned int auto_precharge; 48*91f16700Schasinglulu unsigned int odt_rd_cfg; 49*91f16700Schasinglulu unsigned int odt_wr_cfg; 50*91f16700Schasinglulu unsigned int odt_rtt_norm; 51*91f16700Schasinglulu unsigned int odt_rtt_wr; 52*91f16700Schasinglulu } cs_odt[DDRC_NUM_CS]; 53*91f16700Schasinglulu int ctlr_intlv; 54*91f16700Schasinglulu unsigned int ctlr_intlv_mode; 55*91f16700Schasinglulu unsigned int ba_intlv; 56*91f16700Schasinglulu int addr_hash; 57*91f16700Schasinglulu int ecc_mode; 58*91f16700Schasinglulu int ctlr_init_ecc; 59*91f16700Schasinglulu int self_refresh_in_sleep; 60*91f16700Schasinglulu int self_refresh_irq_en; 61*91f16700Schasinglulu int dynamic_power; 62*91f16700Schasinglulu /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ 63*91f16700Schasinglulu unsigned int data_bus_dimm; 64*91f16700Schasinglulu unsigned int data_bus_used; /* on individual board */ 65*91f16700Schasinglulu unsigned int burst_length; /* BC4, OTF and BL8 */ 66*91f16700Schasinglulu int otf_burst_chop_en; 67*91f16700Schasinglulu int mirrored_dimm; 68*91f16700Schasinglulu int quad_rank_present; 69*91f16700Schasinglulu int output_driver_impedance; 70*91f16700Schasinglulu int ap_en; 71*91f16700Schasinglulu int x4_en; 72*91f16700Schasinglulu 73*91f16700Schasinglulu int caslat_override; 74*91f16700Schasinglulu unsigned int caslat_override_value; 75*91f16700Schasinglulu int addt_lat_override; 76*91f16700Schasinglulu unsigned int addt_lat_override_value; 77*91f16700Schasinglulu 78*91f16700Schasinglulu unsigned int clk_adj; 79*91f16700Schasinglulu unsigned int cpo_sample; 80*91f16700Schasinglulu unsigned int wr_data_delay; 81*91f16700Schasinglulu 82*91f16700Schasinglulu unsigned int cswl_override; 83*91f16700Schasinglulu unsigned int wrlvl_override; 84*91f16700Schasinglulu unsigned int wrlvl_sample; 85*91f16700Schasinglulu unsigned int wrlvl_start; 86*91f16700Schasinglulu unsigned int wrlvl_ctl_2; 87*91f16700Schasinglulu unsigned int wrlvl_ctl_3; 88*91f16700Schasinglulu 89*91f16700Schasinglulu int half_strength_drive_en; 90*91f16700Schasinglulu int twot_en; 91*91f16700Schasinglulu int threet_en; 92*91f16700Schasinglulu unsigned int bstopre; 93*91f16700Schasinglulu unsigned int tfaw_ps; 94*91f16700Schasinglulu 95*91f16700Schasinglulu int rtt_override; 96*91f16700Schasinglulu unsigned int rtt_override_value; 97*91f16700Schasinglulu unsigned int rtt_wr_override_value; 98*91f16700Schasinglulu unsigned int rtt_park; 99*91f16700Schasinglulu 100*91f16700Schasinglulu int auto_self_refresh_en; 101*91f16700Schasinglulu unsigned int sr_it; 102*91f16700Schasinglulu unsigned int ddr_cdr1; 103*91f16700Schasinglulu unsigned int ddr_cdr2; 104*91f16700Schasinglulu 105*91f16700Schasinglulu unsigned int trwt_override; 106*91f16700Schasinglulu unsigned int trwt; 107*91f16700Schasinglulu unsigned int twrt; 108*91f16700Schasinglulu unsigned int trrt; 109*91f16700Schasinglulu unsigned int twwt; 110*91f16700Schasinglulu 111*91f16700Schasinglulu unsigned int vref_phy; 112*91f16700Schasinglulu unsigned int vref_dimm; 113*91f16700Schasinglulu unsigned int odt; 114*91f16700Schasinglulu unsigned int phy_tx_impedance; 115*91f16700Schasinglulu unsigned int phy_atx_impedance; 116*91f16700Schasinglulu unsigned int skip2d; 117*91f16700Schasinglulu }; 118*91f16700Schasinglulu 119*91f16700Schasinglulu #endif /* DDR_OPTS_H */ 120