1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef DDR_IO_H 9*91f16700Schasinglulu #define DDR_IO_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <endian.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <lib/mmio.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define min(a, b) (((a) > (b)) ? (b) : (a)) 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define max(a, b) (((a) > (b)) ? (a) : (b)) 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* macro for memory barrier */ 20*91f16700Schasinglulu #define mb() asm volatile("dsb sy" : : : "memory") 21*91f16700Schasinglulu 22*91f16700Schasinglulu #ifdef NXP_DDR_BE 23*91f16700Schasinglulu #define ddr_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 24*91f16700Schasinglulu #define ddr_out32(a, v) mmio_write_32((uintptr_t)(a),\ 25*91f16700Schasinglulu bswap32(v)) 26*91f16700Schasinglulu #elif defined(NXP_DDR_LE) 27*91f16700Schasinglulu #define ddr_in32(a) mmio_read_32((uintptr_t)(a)) 28*91f16700Schasinglulu #define ddr_out32(a, v) mmio_write_32((uintptr_t)(a), v) 29*91f16700Schasinglulu #else 30*91f16700Schasinglulu #error Please define CCSR DDR register endianness 31*91f16700Schasinglulu #endif 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define ddr_setbits32(a, v) ddr_out32((a), ddr_in32(a) | (v)) 34*91f16700Schasinglulu #define ddr_clrbits32(a, v) ddr_out32((a), ddr_in32(a) & ~(v)) 35*91f16700Schasinglulu #define ddr_clrsetbits32(a, c, s) ddr_out32((a), (ddr_in32(a) & ~(c)) \ 36*91f16700Schasinglulu | (s)) 37*91f16700Schasinglulu 38*91f16700Schasinglulu #endif /* DDR_IO_H */ 39