1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2020-2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef SCFG_H 9*91f16700Schasinglulu #define SCFG_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #ifdef CONFIG_CHASSIS_2 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* SCFG register offsets */ 14*91f16700Schasinglulu #define SCFG_CORE0_SFT_RST_OFFSET 0x0130 15*91f16700Schasinglulu #define SCFG_SNPCNFGCR_OFFSET 0x01A4 16*91f16700Schasinglulu #define SCFG_CORESRENCR_OFFSET 0x0204 17*91f16700Schasinglulu #define SCFG_RVBAR0_0_OFFSET 0x0220 18*91f16700Schasinglulu #define SCFG_RVBAR0_1_OFFSET 0x0224 19*91f16700Schasinglulu #define SCFG_COREBCR_OFFSET 0x0680 20*91f16700Schasinglulu #define SCFG_RETREQCR_OFFSET 0x0424 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define SCFG_COREPMCR_OFFSET 0x042C 23*91f16700Schasinglulu #define COREPMCR_WFIL2 0x1 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188 26*91f16700Schasinglulu #define SCFG_BOOTLOCPTRH_OFFSET 0x0600 27*91f16700Schasinglulu #define SCFG_BOOTLOCPTRL_OFFSET 0x0604 28*91f16700Schasinglulu #define SCFG_SCRATCHRW2_OFFSET 0x0608 29*91f16700Schasinglulu #define SCFG_SCRATCHRW3_OFFSET 0x060C 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* SCFG bit fields */ 32*91f16700Schasinglulu #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 33*91f16700Schasinglulu #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* GIC Address Align Register */ 36*91f16700Schasinglulu #define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000 37*91f16700Schasinglulu #define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000 38*91f16700Schasinglulu #define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0 39*91f16700Schasinglulu 40*91f16700Schasinglulu #endif /* CONFIG_CHASSIS_2 */ 41*91f16700Schasinglulu 42*91f16700Schasinglulu #ifndef __ASSEMBLER__ 43*91f16700Schasinglulu #include <endian.h> 44*91f16700Schasinglulu #include <lib/mmio.h> 45*91f16700Schasinglulu 46*91f16700Schasinglulu #ifdef NXP_SCFG_BE 47*91f16700Schasinglulu #define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 48*91f16700Schasinglulu #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 49*91f16700Schasinglulu #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) 50*91f16700Schasinglulu #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) 51*91f16700Schasinglulu #define scfg_clrsetbits32(a, clear, set) \ 52*91f16700Schasinglulu mmio_clrsetbits_32((uintptr_t)(a), clear, set) 53*91f16700Schasinglulu #elif defined(NXP_SCFG_LE) 54*91f16700Schasinglulu #define scfg_in32(a) mmio_read_32((uintptr_t)(a)) 55*91f16700Schasinglulu #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v) 56*91f16700Schasinglulu #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) 57*91f16700Schasinglulu #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) 58*91f16700Schasinglulu #define scfg_clrsetbits32(a, clear, set) \ 59*91f16700Schasinglulu mmio_clrsetbits_32((uintptr_t)(a), clear, set) 60*91f16700Schasinglulu #else 61*91f16700Schasinglulu #error Please define CCSR SCFG register endianness 62*91f16700Schasinglulu #endif 63*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 64*91f16700Schasinglulu 65*91f16700Schasinglulu #endif /* SCFG_H */ 66