1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2020-2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef DCFG_LSCH3_H 9*91f16700Schasinglulu #define DCFG_LSCH3_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu /* dcfg block register offsets and bitfields */ 12*91f16700Schasinglulu #define DCFG_PORSR1_OFFSET 0x00 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define DCFG_DEVDISR1_OFFSET 0x70 15*91f16700Schasinglulu #define DCFG_DEVDISR1_SEC (1 << 22) 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define DCFG_DEVDISR2_OFFSET 0x74 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define DCFG_DEVDISR3_OFFSET 0x78 20*91f16700Schasinglulu #define DCFG_DEVDISR3_QBMAIN (1 << 12) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define DCFG_DEVDISR4_OFFSET 0x7C 23*91f16700Schasinglulu #define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define DCFG_DEVDISR5_OFFSET 0x80 26*91f16700Schasinglulu #define DISR5_DDRC1_MASK 0x1 27*91f16700Schasinglulu #define DISR5_DDRC2_MASK 0x2 28*91f16700Schasinglulu #define DISR5_OCRAM_MASK 0x1000 29*91f16700Schasinglulu #define DEVDISR5_MASK_ALL_MEM 0x00001003 30*91f16700Schasinglulu #define DEVDISR5_MASK_DDR 0x00000003 31*91f16700Schasinglulu #define DEVDISR5_MASK_DBG 0x00000400 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define DCFG_DEVDISR6_OFFSET 0x84 34*91f16700Schasinglulu //#define DEVDISR6_MASK 0x00000001 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define DCFG_COREDISR_OFFSET 0x94 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define DCFG_SVR_OFFSET 0x0A4 39*91f16700Schasinglulu #define SVR_MFR_ID_MASK 0xF0000000 40*91f16700Schasinglulu #define SVR_MFR_ID_SHIFT 28 41*91f16700Schasinglulu #define SVR_FAMILY_MASK 0xF000000 42*91f16700Schasinglulu #define SVR_FAMILY_SHIFT 24 43*91f16700Schasinglulu #define SVR_DEV_ID_MASK 0x3F0000 44*91f16700Schasinglulu #define SVR_DEV_ID_SHIFT 16 45*91f16700Schasinglulu #define SVR_PERSONALITY_MASK 0x3E00 46*91f16700Schasinglulu #define SVR_PERSONALITY_SHIFT 9 47*91f16700Schasinglulu #define SVR_SEC_MASK 0x100 48*91f16700Schasinglulu #define SVR_SEC_SHIFT 8 49*91f16700Schasinglulu #define SVR_MAJ_VER_MASK 0xF0 50*91f16700Schasinglulu #define SVR_MAJ_VER_SHIFT 4 51*91f16700Schasinglulu #define SVR_MIN_VER_MASK 0xF 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define RCWSR0_OFFSET 0x100 54*91f16700Schasinglulu #define RCWSR0_SYS_PLL_RAT_SHIFT 2 55*91f16700Schasinglulu #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 56*91f16700Schasinglulu #define RCWSR0_MEM_PLL_RAT_SHIFT 10 57*91f16700Schasinglulu #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 58*91f16700Schasinglulu #define RCWSR0_MEM2_PLL_RAT_SHIFT 18 59*91f16700Schasinglulu #define RCWSR0_MEM2_PLL_RAT_MASK 0x3f 60*91f16700Schasinglulu 61*91f16700Schasinglulu #define RCWSR5_OFFSET 0x110 62*91f16700Schasinglulu #define RCWSR9_OFFSET 0x120 63*91f16700Schasinglulu #define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET 64*91f16700Schasinglulu #define RCWSR_SBEN_MASK 0x1 65*91f16700Schasinglulu #define RCWSR_SBEN_SHIFT 10 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define RCW_SR27_OFFSET 0x168 68*91f16700Schasinglulu /* DCFG register to dump error code */ 69*91f16700Schasinglulu #define DCFG_SCRATCH4_OFFSET 0x20C 70*91f16700Schasinglulu #define DCFG_SCRATCHRW5_OFFSET 0x210 71*91f16700Schasinglulu #define DCFG_SCRATCHRW6_OFFSET 0x214 72*91f16700Schasinglulu #define DCFG_SCRATCHRW7_OFFSET 0x218 73*91f16700Schasinglulu #define DCFG_BOOTLOCPTRL_OFFSET 0x400 74*91f16700Schasinglulu #define DCFG_BOOTLOCPTRH_OFFSET 0x404 75*91f16700Schasinglulu #define DCFG_COREDISABLEDSR_OFFSET 0x990 76*91f16700Schasinglulu 77*91f16700Schasinglulu /* Reset module bit field */ 78*91f16700Schasinglulu #define RSTCR_RESET_REQ 0x2 79*91f16700Schasinglulu 80*91f16700Schasinglulu #endif /* DCFG_LSCH3_H */ 81