1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2018-2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef DCFG_H 9*91f16700Schasinglulu #define DCFG_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <endian.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #if defined(CONFIG_CHASSIS_2) 14*91f16700Schasinglulu #include <dcfg_lsch2.h> 15*91f16700Schasinglulu #elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) 16*91f16700Schasinglulu #include <dcfg_lsch3.h> 17*91f16700Schasinglulu #endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu #ifdef NXP_GUR_BE 20*91f16700Schasinglulu #define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 21*91f16700Schasinglulu #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 22*91f16700Schasinglulu #elif defined(NXP_GUR_LE) 23*91f16700Schasinglulu #define gur_in32(a) mmio_read_32((uintptr_t)(a)) 24*91f16700Schasinglulu #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v) 25*91f16700Schasinglulu #else 26*91f16700Schasinglulu #error Please define CCSR GUR register endianness 27*91f16700Schasinglulu #endif 28*91f16700Schasinglulu 29*91f16700Schasinglulu typedef struct { 30*91f16700Schasinglulu union { 31*91f16700Schasinglulu uint32_t val; 32*91f16700Schasinglulu struct { 33*91f16700Schasinglulu uint32_t min_ver:4; 34*91f16700Schasinglulu uint32_t maj_ver:4; 35*91f16700Schasinglulu #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 36*91f16700Schasinglulu uint32_t personality:6; 37*91f16700Schasinglulu uint32_t rsv1:2; 38*91f16700Schasinglulu #elif defined(CONFIG_CHASSIS_2) 39*91f16700Schasinglulu uint32_t personality:8; 40*91f16700Schasinglulu 41*91f16700Schasinglulu #endif 42*91f16700Schasinglulu #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 43*91f16700Schasinglulu uint32_t dev_id:6; 44*91f16700Schasinglulu uint32_t rsv2:2; 45*91f16700Schasinglulu uint32_t family:4; 46*91f16700Schasinglulu #elif defined(CONFIG_CHASSIS_2) 47*91f16700Schasinglulu uint32_t dev_id:12; 48*91f16700Schasinglulu #endif 49*91f16700Schasinglulu uint32_t mfr_id; 50*91f16700Schasinglulu } __packed bf; 51*91f16700Schasinglulu struct { 52*91f16700Schasinglulu uint32_t maj_min:8; 53*91f16700Schasinglulu uint32_t version; /* SoC version without major and minor info */ 54*91f16700Schasinglulu } __packed bf_ver; 55*91f16700Schasinglulu } __packed svr_reg; 56*91f16700Schasinglulu bool sec_enabled; 57*91f16700Schasinglulu bool is_populated; 58*91f16700Schasinglulu } soc_info_t; 59*91f16700Schasinglulu 60*91f16700Schasinglulu typedef struct { 61*91f16700Schasinglulu bool is_populated; 62*91f16700Schasinglulu uint8_t ocram_present; 63*91f16700Schasinglulu uint8_t ddrc1_present; 64*91f16700Schasinglulu #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 65*91f16700Schasinglulu uint8_t ddrc2_present; 66*91f16700Schasinglulu #endif 67*91f16700Schasinglulu } devdisr5_info_t; 68*91f16700Schasinglulu 69*91f16700Schasinglulu typedef struct { 70*91f16700Schasinglulu uint32_t porsr1; 71*91f16700Schasinglulu uintptr_t g_nxp_dcfg_addr; 72*91f16700Schasinglulu unsigned long nxp_sysclk_freq; 73*91f16700Schasinglulu unsigned long nxp_ddrclk_freq; 74*91f16700Schasinglulu unsigned int nxp_plat_clk_divider; 75*91f16700Schasinglulu } dcfg_init_info_t; 76*91f16700Schasinglulu 77*91f16700Schasinglulu 78*91f16700Schasinglulu struct sysinfo { 79*91f16700Schasinglulu unsigned long freq_platform; 80*91f16700Schasinglulu unsigned long freq_ddr_pll0; 81*91f16700Schasinglulu unsigned long freq_ddr_pll1; 82*91f16700Schasinglulu }; 83*91f16700Schasinglulu 84*91f16700Schasinglulu int get_clocks(struct sysinfo *sys); 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* Read the PORSR1 register */ 87*91f16700Schasinglulu uint32_t read_reg_porsr1(void); 88*91f16700Schasinglulu 89*91f16700Schasinglulu /******************************************************************************* 90*91f16700Schasinglulu * Returns true if secur eboot is enabled on board 91*91f16700Schasinglulu * mode = 0 (development mode - sb_en = 1) 92*91f16700Schasinglulu * mode = 1 (production mode - ITS = 1) 93*91f16700Schasinglulu ******************************************************************************/ 94*91f16700Schasinglulu bool check_boot_mode_secure(uint32_t *mode); 95*91f16700Schasinglulu 96*91f16700Schasinglulu const soc_info_t *get_soc_info(void); 97*91f16700Schasinglulu const devdisr5_info_t *get_devdisr5_info(void); 98*91f16700Schasinglulu 99*91f16700Schasinglulu void dcfg_init(dcfg_init_info_t *dcfg_init_data); 100*91f16700Schasinglulu bool is_sec_enabled(void); 101*91f16700Schasinglulu 102*91f16700Schasinglulu void error_handler(int error_code); 103*91f16700Schasinglulu #endif /* DCFG_H */ 104