1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2018-2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef CAAM_IO_H 9*91f16700Schasinglulu #define CAAM_IO_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <endian.h> 12*91f16700Schasinglulu #include <lib/mmio.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu typedef unsigned long long phys_addr_t; 15*91f16700Schasinglulu typedef unsigned long long phys_size_t; 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* Return higher 32 bits of physical address */ 18*91f16700Schasinglulu #define PHYS_ADDR_HI(phys_addr) \ 19*91f16700Schasinglulu (uint32_t)(((uint64_t)phys_addr) >> 32) 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* Return lower 32 bits of physical address */ 22*91f16700Schasinglulu #define PHYS_ADDR_LO(phys_addr) \ 23*91f16700Schasinglulu (uint32_t)(((uint64_t)phys_addr) & 0xFFFFFFFF) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #ifdef NXP_SEC_BE 26*91f16700Schasinglulu #define sec_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 27*91f16700Schasinglulu #define sec_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 28*91f16700Schasinglulu #define sec_in64(addr) ( \ 29*91f16700Schasinglulu ((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \ 30*91f16700Schasinglulu (sec_in32(((uintptr_t)(addr)) + 4))) 31*91f16700Schasinglulu #define sec_out64(addr, val) ({ \ 32*91f16700Schasinglulu sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \ 33*91f16700Schasinglulu sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); }) 34*91f16700Schasinglulu #elif defined(NXP_SEC_LE) 35*91f16700Schasinglulu #define sec_in32(a) mmio_read_32((uintptr_t)(a)) 36*91f16700Schasinglulu #define sec_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) 37*91f16700Schasinglulu #define sec_in64(addr) ( \ 38*91f16700Schasinglulu ((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \ 39*91f16700Schasinglulu (sec_in32((uintptr_t)(addr)))) 40*91f16700Schasinglulu #define sec_out64(addr, val) ({ \ 41*91f16700Schasinglulu sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)((val) >> 32)); \ 42*91f16700Schasinglulu sec_out32(((uintptr_t)(addr)), (uint32_t)(val)); }) 43*91f16700Schasinglulu #else 44*91f16700Schasinglulu #error Please define CCSR SEC register endianness 45*91f16700Schasinglulu #endif 46*91f16700Schasinglulu 47*91f16700Schasinglulu static inline void *ptov(phys_addr_t *ptr) 48*91f16700Schasinglulu { 49*91f16700Schasinglulu return (void *)ptr; 50*91f16700Schasinglulu } 51*91f16700Schasinglulu 52*91f16700Schasinglulu static inline phys_addr_t *vtop(void *ptr) 53*91f16700Schasinglulu { 54*91f16700Schasinglulu return (phys_addr_t *)ptr; 55*91f16700Schasinglulu } 56*91f16700Schasinglulu #endif /* CAAM_IO_H */ 57