1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu /* CP110 Marvell SoC driver */ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #ifndef CP110_SETUP_H 11*91f16700Schasinglulu #define CP110_SETUP_H 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <lib/mmio.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <mvebu_def.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_OFFSET + 0x40) 18*91f16700Schasinglulu #define MVEBU_DEVICE_ID_OFFSET (0) 19*91f16700Schasinglulu #define MVEBU_DEVICE_ID_MASK (0xffff << MVEBU_DEVICE_ID_OFFSET) 20*91f16700Schasinglulu #define MVEBU_DEVICE_REV_OFFSET (16) 21*91f16700Schasinglulu #define MVEBU_DEVICE_REV_MASK (0xf << MVEBU_DEVICE_REV_OFFSET) 22*91f16700Schasinglulu #define MVEBU_70X0_DEV_ID (0x7040) 23*91f16700Schasinglulu #define MVEBU_70X0_CP115_DEV_ID (0x7045) 24*91f16700Schasinglulu #define MVEBU_3900_DEV_ID (0x6025) 25*91f16700Schasinglulu #define MVEBU_80X0_DEV_ID (0x8040) 26*91f16700Schasinglulu #define MVEBU_80X0_CP115_DEV_ID (0x8045) 27*91f16700Schasinglulu #define MVEBU_CN9130_DEV_ID (0x7025) 28*91f16700Schasinglulu #define MVEBU_CP110_SA_DEV_ID (0x110) 29*91f16700Schasinglulu #define MVEBU_CP110_REF_ID_A1 1 30*91f16700Schasinglulu #define MVEBU_CP110_REF_ID_A2 2 31*91f16700Schasinglulu #define MAX_STREAM_ID_PER_CP (0x10) 32*91f16700Schasinglulu #define STREAM_ID_BASE (0x40) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define MVEBU_SECUREBOOT_CTRL_REG (MVEBU_RFU_BASE + 0x4730) 35*91f16700Schasinglulu #define MVEBU_SECUREBOOT_EN_MASK BIT(0) 36*91f16700Schasinglulu 37*91f16700Schasinglulu static inline uint32_t cp110_device_id_get(uintptr_t base) 38*91f16700Schasinglulu { 39*91f16700Schasinglulu /* Returns: 40*91f16700Schasinglulu * - MVEBU_70X0_DEV_ID for A70X0 family 41*91f16700Schasinglulu * - MVEBU_80X0_DEV_ID for A80X0 family 42*91f16700Schasinglulu * - MVEBU_CP110_SA_DEV_ID for CP that connected stand alone 43*91f16700Schasinglulu */ 44*91f16700Schasinglulu return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) >> 45*91f16700Schasinglulu MVEBU_DEVICE_ID_OFFSET) & 46*91f16700Schasinglulu MVEBU_DEVICE_ID_MASK; 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu static inline uint32_t cp110_rev_id_get(uintptr_t base) 50*91f16700Schasinglulu { 51*91f16700Schasinglulu return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) & 52*91f16700Schasinglulu MVEBU_DEVICE_REV_MASK) >> 53*91f16700Schasinglulu MVEBU_DEVICE_REV_OFFSET; 54*91f16700Schasinglulu } 55*91f16700Schasinglulu 56*91f16700Schasinglulu static inline uint32_t is_secure(void) 57*91f16700Schasinglulu { 58*91f16700Schasinglulu return !!(mmio_read_32(MVEBU_SECUREBOOT_CTRL_REG) & 59*91f16700Schasinglulu MVEBU_SECUREBOOT_EN_MASK); 60*91f16700Schasinglulu } 61*91f16700Schasinglulu 62*91f16700Schasinglulu void cp110_init(uintptr_t cp110_base, uint32_t stream_id); 63*91f16700Schasinglulu void cp110_ble_init(uintptr_t cp110_base); 64*91f16700Schasinglulu void cp110_amb_init(uintptr_t base); 65*91f16700Schasinglulu 66*91f16700Schasinglulu #endif /* CP110_SETUP_H */ 67