1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2017 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu #ifndef ARO_H 8*91f16700Schasinglulu #define ARO_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu enum hws_freq { 11*91f16700Schasinglulu CPU_FREQ_2000, 12*91f16700Schasinglulu CPU_FREQ_1800, 13*91f16700Schasinglulu CPU_FREQ_1600, 14*91f16700Schasinglulu CPU_FREQ_1400, 15*91f16700Schasinglulu CPU_FREQ_1300, 16*91f16700Schasinglulu CPU_FREQ_1200, 17*91f16700Schasinglulu CPU_FREQ_1000, 18*91f16700Schasinglulu CPU_FREQ_600, 19*91f16700Schasinglulu CPU_FREQ_800, 20*91f16700Schasinglulu DDR_FREQ_LAST, 21*91f16700Schasinglulu DDR_FREQ_SAR 22*91f16700Schasinglulu }; 23*91f16700Schasinglulu 24*91f16700Schasinglulu #include <mvebu_def.h> 25*91f16700Schasinglulu 26*91f16700Schasinglulu enum cpu_clock_freq_mode { 27*91f16700Schasinglulu CPU_2000_DDR_1200_RCLK_1200 = 0x0, 28*91f16700Schasinglulu CPU_2000_DDR_1050_RCLK_1050 = 0x1, 29*91f16700Schasinglulu CPU_1600_DDR_800_RCLK_800 = 0x4, 30*91f16700Schasinglulu CPU_2200_DDR_1200_RCLK_1200 = 0x6, 31*91f16700Schasinglulu CPU_1800_DDR_1050_RCLK_1050 = 0x7, 32*91f16700Schasinglulu CPU_1600_DDR_900_RCLK_900 = 0x0B, 33*91f16700Schasinglulu CPU_1600_DDR_1050_RCLK_1050 = 0x0D, 34*91f16700Schasinglulu CPU_1600_DDR_1200_RCLK_1200 = 0x0D, 35*91f16700Schasinglulu CPU_1600_DDR_900_RCLK_900_2 = 0x0E, 36*91f16700Schasinglulu CPU_1000_DDR_650_RCLK_650 = 0x13, 37*91f16700Schasinglulu CPU_1300_DDR_800_RCLK_800 = 0x14, 38*91f16700Schasinglulu CPU_1300_DDR_650_RCLK_650 = 0x17, 39*91f16700Schasinglulu CPU_1200_DDR_800_RCLK_800 = 0x19, 40*91f16700Schasinglulu CPU_1400_DDR_800_RCLK_800 = 0x1a, 41*91f16700Schasinglulu CPU_600_DDR_800_RCLK_800 = 0x1B, 42*91f16700Schasinglulu CPU_800_DDR_800_RCLK_800 = 0x1C, 43*91f16700Schasinglulu CPU_1000_DDR_800_RCLK_800 = 0x1D, 44*91f16700Schasinglulu CPU_DDR_RCLK_INVALID 45*91f16700Schasinglulu }; 46*91f16700Schasinglulu 47*91f16700Schasinglulu int init_aro(void); 48*91f16700Schasinglulu 49*91f16700Schasinglulu #endif /* ARO_H */ 50