1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016 - 2021, Broadcom 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MDIO_H 8*91f16700Schasinglulu #define MDIO_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define CMIC_MIIM_PARAM (PLAT_CMIC_MIIM_BASE + 0x23cU) 11*91f16700Schasinglulu #define MDIO_PARAM_MIIM_CYCLE 29U 12*91f16700Schasinglulu #define MDIO_PARAM_INTERNAL_SEL 25U 13*91f16700Schasinglulu #define MDIO_PARAM_BUSID 22U 14*91f16700Schasinglulu #define MDIO_PARAM_BUSID_MASK 0x7U 15*91f16700Schasinglulu #define MDIO_PARAM_C45_SEL 21U 16*91f16700Schasinglulu #define MDIO_PARAM_PHYID 16U 17*91f16700Schasinglulu #define MDIO_PARAM_PHYID_MASK 0x1FU 18*91f16700Schasinglulu #define MDIO_PARAM_DATA 0U 19*91f16700Schasinglulu #define MDIO_PARAM_DATA_MASK 0xFFFFU 20*91f16700Schasinglulu #define CMIC_MIIM_READ_DATA (PLAT_CMIC_MIIM_BASE + 0x240U) 21*91f16700Schasinglulu #define MDIO_READ_DATA_MASK 0xffffU 22*91f16700Schasinglulu #define CMIC_MIIM_ADDRESS (PLAT_CMIC_MIIM_BASE + 0x244U) 23*91f16700Schasinglulu #define CMIC_MIIM_CTRL (PLAT_CMIC_MIIM_BASE + 0x248U) 24*91f16700Schasinglulu #define MDIO_CTRL_WRITE_OP 0x1U 25*91f16700Schasinglulu #define MDIO_CTRL_READ_OP 0x2U 26*91f16700Schasinglulu #define CMIC_MIIM_STAT (PLAT_CMIC_MIIM_BASE + 0x24cU) 27*91f16700Schasinglulu #define MDIO_STAT_DONE 1U 28*91f16700Schasinglulu 29*91f16700Schasinglulu int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val); 30*91f16700Schasinglulu int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg); 31*91f16700Schasinglulu #endif /* MDIO_H */ 32