1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016 - 2020, Broadcom 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CHAL_SD_H 8*91f16700Schasinglulu #define CHAL_SD_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stddef.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define BASE_CLK_FREQ (200 * 1000 * 1000) 13*91f16700Schasinglulu #define INIT_CLK_FREQ (400 * 1000) 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define SD_ERROR_RECOVERABLE 0 16*91f16700Schasinglulu #define SD_ERROR_NON_RECOVERABLE 1 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define SD_OK 0 19*91f16700Schasinglulu #define SD_FAIL (-1) 20*91f16700Schasinglulu #define SD_INVALID_HANDLE (-2) 21*91f16700Schasinglulu #define SD_CEATA_INIT_ERROR (-3) 22*91f16700Schasinglulu #define SD_RESET_ERROR (-4) 23*91f16700Schasinglulu #define SD_CARD_INIT_ERROR (-5) 24*91f16700Schasinglulu #define SD_INV_DATA_WIDTH (-6) 25*91f16700Schasinglulu #define SD_SET_BUS_WIDTH_ERROR (-7) 26*91f16700Schasinglulu #define SD_DMA_NOT_SUPPORT (-8) 27*91f16700Schasinglulu #define SD_SDIO_READ_ERROR (-9) 28*91f16700Schasinglulu #define SD_SDIO_WRITE_ERROR (-10) 29*91f16700Schasinglulu #define SD_WRITE_ERROR (-11) 30*91f16700Schasinglulu #define SD_READ_ERROR (-12) 31*91f16700Schasinglulu #define SD_READ_SIZE_ERROR (-13) 32*91f16700Schasinglulu #define SD_RW_ADDRESS_ERROR (-14) 33*91f16700Schasinglulu #define SD_XFER_ADDRESS_ERROR (-15) 34*91f16700Schasinglulu #define SD_DATA_XFER_ADDR_ERROR (-16) 35*91f16700Schasinglulu #define SD_DATA_XFER_ERROR (-17) 36*91f16700Schasinglulu #define SD_WRITE_SIZE_ERROR (-18) 37*91f16700Schasinglulu #define SD_CMD_STATUS_UPDATE_ERR (-19) 38*91f16700Schasinglulu #define SD_CMD12_ERROR (-20) 39*91f16700Schasinglulu #define SD_CMD_DATA_ERROR (-21) 40*91f16700Schasinglulu #define SD_CMD_TIMEOUT (-22) 41*91f16700Schasinglulu #define SD_CMD_NO_RESPONSE (-22) 42*91f16700Schasinglulu #define SD_CMD_ABORT_ERROR (-23) 43*91f16700Schasinglulu #define SD_CMD_INVALID (-24) 44*91f16700Schasinglulu #define SD_CMD_RESUME_ERROR (-25) 45*91f16700Schasinglulu #define SD_CMD_ERR_INVALID_RESPONSE (-26) 46*91f16700Schasinglulu #define SD_WAIT_TIMEOUT (-27) 47*91f16700Schasinglulu #define SD_READ_TIMEOUT (-28) 48*91f16700Schasinglulu #define SD_CEATA_REST_ERROR (-29) 49*91f16700Schasinglulu #define SD_INIT_CAED_FAILED (-30) 50*91f16700Schasinglulu #define SD_ERROR_CLOCK_OFFLIMIT (-31) 51*91f16700Schasinglulu #define SD_INV_SLOT (-32) 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define SD_NOR_INTERRUPTS 0x000000FF 54*91f16700Schasinglulu #define SD_ERR_INTERRUPTS 0x03FF0000 55*91f16700Schasinglulu #define SD_CMD_ERROR_INT 0x010F0000 56*91f16700Schasinglulu #define SD_DAT_ERROR_INT 0x02F00000 57*91f16700Schasinglulu #define SD_DAT_TIMEOUT 0x00100000 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* Operation modes */ 60*91f16700Schasinglulu #define SD_PIO_MODE 0 61*91f16700Schasinglulu #define SD_INT_MODE 1 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* Support both ADMA and SDMA (for version 2.0 and above) */ 64*91f16700Schasinglulu #define SD_DMA_OFF 0 65*91f16700Schasinglulu #define SD_DMA_SDMA 1 66*91f16700Schasinglulu #define SD_DMA_ADMA 2 67*91f16700Schasinglulu 68*91f16700Schasinglulu #define SD_NORMAL_SPEED 0 69*91f16700Schasinglulu #define SD_HIGH_SPEED 1 70*91f16700Schasinglulu 71*91f16700Schasinglulu #define SD_XFER_CARD_TO_HOST 3 72*91f16700Schasinglulu #define SD_XFER_HOST_TO_CARD 4 73*91f16700Schasinglulu 74*91f16700Schasinglulu #define SD_CARD_DETECT_AUTO 0 75*91f16700Schasinglulu #define SD_CARD_DETECT_SD 1 76*91f16700Schasinglulu #define SD_CARD_DETECT_SDIO 2 77*91f16700Schasinglulu #define SD_CARD_DETECT_MMC 3 78*91f16700Schasinglulu #define SD_CARD_DETECT_CEATA 4 79*91f16700Schasinglulu 80*91f16700Schasinglulu #define SD_ABORT_SYNC_MODE 0 81*91f16700Schasinglulu #define SD_ABORT_ASYNC_MODE 1 82*91f16700Schasinglulu 83*91f16700Schasinglulu #define SD_CMD_ERROR_FLAGS (0x18F << 16) 84*91f16700Schasinglulu #define SD_DATA_ERROR_FLAGS (0x70 << 16) 85*91f16700Schasinglulu #define SD_AUTO_CMD12_ERROR_FLAGS (0x9F) 86*91f16700Schasinglulu 87*91f16700Schasinglulu #define SD_CARD_STATUS_ERROR 0x10000000 88*91f16700Schasinglulu #define SD_CMD_MISSING 0x80000000 89*91f16700Schasinglulu #define SD_ERROR_INT 0x8000 90*91f16700Schasinglulu 91*91f16700Schasinglulu #define SD_TRAN_HIGH_SPEED 0x32 92*91f16700Schasinglulu #define SD_CARD_HIGH_CAPACITY 0x40000000 93*91f16700Schasinglulu #define SD_CARD_POWER_UP_STATUS 0x80000000 94*91f16700Schasinglulu 95*91f16700Schasinglulu #define SD_HOST_CORE_TIMEOUT 0x0E 96*91f16700Schasinglulu 97*91f16700Schasinglulu /* SD CARD and Host Controllers bus width */ 98*91f16700Schasinglulu #define SD_BUS_DATA_WIDTH_1BIT 0x00 99*91f16700Schasinglulu #define SD_BUS_DATA_WIDTH_4BIT 0x02 100*91f16700Schasinglulu #define SD_BUS_DATA_WIDTH_8BIT 0x20 101*91f16700Schasinglulu 102*91f16700Schasinglulu /* dma boundary settings */ 103*91f16700Schasinglulu #define SD_DMA_BOUNDARY_4K 0 104*91f16700Schasinglulu #define SD_DMA_BOUNDARY_8K (1 << 12) 105*91f16700Schasinglulu #define SD_DMA_BOUNDARY_16K (2 << 12) 106*91f16700Schasinglulu #define SD_DMA_BOUNDARY_32K (3 << 12) 107*91f16700Schasinglulu #define SD_DMA_BOUNDARY_64K (4 << 12) 108*91f16700Schasinglulu #define SD_DMA_BOUNDARY_128K (5 << 12) 109*91f16700Schasinglulu #define SD_DMA_BOUNDARY_256K (6 << 12) 110*91f16700Schasinglulu #define SD_DMA_BOUNDARY_512K (7 << 12) 111*91f16700Schasinglulu 112*91f16700Schasinglulu #define SD_CMDR_CMD_NORMAL 0x00000000 113*91f16700Schasinglulu #define SD_CMDR_CMD_SUSPEND 0x00400000 114*91f16700Schasinglulu #define SD_CMDR_CMD_RESUME 0x00800000 115*91f16700Schasinglulu #define SD_CMDR_CMD_ABORT 0x00c00000 116*91f16700Schasinglulu 117*91f16700Schasinglulu #define SD_CMDR_RSP_TYPE_NONE 0x0 118*91f16700Schasinglulu #define SD_CMDR_RSP_TYPE_R2 0x1 119*91f16700Schasinglulu #define SD_CMDR_RSP_TYPE_R3_4 0x2 120*91f16700Schasinglulu #define SD_CMDR_RSP_TYPE_R1_5_6 0x2 121*91f16700Schasinglulu #define SD_CMDR_RSP_TYPE_R1b_5b 0x3 122*91f16700Schasinglulu #define SD_CMDR_RSP_TYPE_S 16 123*91f16700Schasinglulu 124*91f16700Schasinglulu struct sd_ctrl_info { 125*91f16700Schasinglulu uint32_t blkReg; /* current block register cache value */ 126*91f16700Schasinglulu uint32_t cmdReg; /* current command register cache value */ 127*91f16700Schasinglulu uint32_t argReg; /* current argument register cache value */ 128*91f16700Schasinglulu uint32_t cmdIndex; /* current command index */ 129*91f16700Schasinglulu uint32_t cmdStatus; /* current command status, cmd/data compelete */ 130*91f16700Schasinglulu uint16_t rca; /* relative card address */ 131*91f16700Schasinglulu uint32_t ocr; /* operation codition */ 132*91f16700Schasinglulu uint32_t eventList; /* events list */ 133*91f16700Schasinglulu uint32_t blkGapEnable; 134*91f16700Schasinglulu 135*91f16700Schasinglulu uint32_t capability; /* controller's capbilities */ 136*91f16700Schasinglulu uint32_t maxCurrent; /* maximum current supported */ 137*91f16700Schasinglulu uint32_t present; /* if card is inserted or removed */ 138*91f16700Schasinglulu uint32_t version; /* SD spec version 1.0 or 2.0 */ 139*91f16700Schasinglulu uint32_t vendor; /* vendor number */ 140*91f16700Schasinglulu 141*91f16700Schasinglulu uintptr_t sdRegBaseAddr; /* sdio control registers */ 142*91f16700Schasinglulu uintptr_t hostRegBaseAddr; /* SD Host control registers */ 143*91f16700Schasinglulu }; 144*91f16700Schasinglulu 145*91f16700Schasinglulu struct sd_cfg { 146*91f16700Schasinglulu uint32_t mode; /* interrupt or polling */ 147*91f16700Schasinglulu uint32_t dma; /* dma enabled or disabled */ 148*91f16700Schasinglulu uint32_t retryLimit; /* command retry limit */ 149*91f16700Schasinglulu uint32_t speedMode; /* speed mode, 0 standard, 1 high speed */ 150*91f16700Schasinglulu uint32_t voltage; /* voltage level */ 151*91f16700Schasinglulu uint32_t blockSize; /* access block size (512 for HC card) */ 152*91f16700Schasinglulu uint32_t dmaBoundary; /* dma address boundary */ 153*91f16700Schasinglulu uint32_t detSignal; /* card det signal src, for test purpose only */ 154*91f16700Schasinglulu uint32_t rdWaiting; 155*91f16700Schasinglulu uint32_t wakeupOut; 156*91f16700Schasinglulu uint32_t wakeupIn; 157*91f16700Schasinglulu uint32_t wakeupInt; 158*91f16700Schasinglulu uint32_t wfe_retry; 159*91f16700Schasinglulu uint32_t gapInt; 160*91f16700Schasinglulu uint32_t readWait; 161*91f16700Schasinglulu uint32_t led; 162*91f16700Schasinglulu }; 163*91f16700Schasinglulu 164*91f16700Schasinglulu struct sd_dev { 165*91f16700Schasinglulu struct sd_cfg cfg; /* SD configuration */ 166*91f16700Schasinglulu struct sd_ctrl_info ctrl; /* SD info */ 167*91f16700Schasinglulu }; 168*91f16700Schasinglulu 169*91f16700Schasinglulu int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode, 170*91f16700Schasinglulu uint32_t sdBase, uint32_t hostBase); 171*91f16700Schasinglulu int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed, 172*91f16700Schasinglulu uint32_t retry, uint32_t boundary, 173*91f16700Schasinglulu uint32_t blkSize, uint32_t dma); 174*91f16700Schasinglulu int32_t chal_sd_stop(void); 175*91f16700Schasinglulu int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode); 176*91f16700Schasinglulu uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *handle); 177*91f16700Schasinglulu int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width); 178*91f16700Schasinglulu int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex, 179*91f16700Schasinglulu uint32_t arg, uint32_t options); 180*91f16700Schasinglulu int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address); 181*91f16700Schasinglulu int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle, 182*91f16700Schasinglulu uint32_t div_ctrl_setting, uint32_t on); 183*91f16700Schasinglulu uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq); 184*91f16700Schasinglulu int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data, 185*91f16700Schasinglulu uint32_t length, int32_t dir); 186*91f16700Schasinglulu int32_t chal_sd_write_buffer(CHAL_HANDLE *sdHandle, uint32_t length, 187*91f16700Schasinglulu uint8_t *data); 188*91f16700Schasinglulu int32_t chal_sd_read_buffer(CHAL_HANDLE *sdHandle, uint32_t length, 189*91f16700Schasinglulu uint8_t *data); 190*91f16700Schasinglulu int32_t chal_sd_reset_line(CHAL_HANDLE *sdHandle, uint32_t line); 191*91f16700Schasinglulu int32_t chal_sd_get_response(CHAL_HANDLE *sdHandle, uint32_t *resp); 192*91f16700Schasinglulu int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sdHandle); 193*91f16700Schasinglulu int32_t chal_sd_get_irq_status(CHAL_HANDLE *sdHandle); 194*91f16700Schasinglulu int32_t chal_sd_clear_irq(CHAL_HANDLE *sdHandle, uint32_t mask); 195*91f16700Schasinglulu uint32_t chal_sd_get_present_status(CHAL_HANDLE *sdHandle); 196*91f16700Schasinglulu int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sdHandle); 197*91f16700Schasinglulu void chal_sd_set_speed(CHAL_HANDLE *sdHandle, uint32_t speed); 198*91f16700Schasinglulu int32_t chal_sd_check_cap(CHAL_HANDLE *sdHandle, uint32_t cap); 199*91f16700Schasinglulu void chal_sd_set_irq_signal(CHAL_HANDLE *sdHandle, uint32_t mask, 200*91f16700Schasinglulu uint32_t state); 201*91f16700Schasinglulu void chal_sd_dump_fifo(CHAL_HANDLE *sdHandle); 202*91f16700Schasinglulu #endif /* CHAL_SD_H */ 203