1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015 - 2020, Broadcom 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef DMU_H 8*91f16700Schasinglulu #define DMU_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Clock field should be 2 bits only */ 11*91f16700Schasinglulu #define CLKCONFIG_MASK 0x3 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* argument */ 14*91f16700Schasinglulu struct DmuBlockEnable { 15*91f16700Schasinglulu uint32_t sotp:1; 16*91f16700Schasinglulu uint32_t pka_rng:1; 17*91f16700Schasinglulu uint32_t crypto:1; 18*91f16700Schasinglulu uint32_t spl:1; 19*91f16700Schasinglulu uint32_t cdru_vgm:1; 20*91f16700Schasinglulu uint32_t apbs_s0_idm:1; 21*91f16700Schasinglulu uint32_t smau_s0_idm:1; 22*91f16700Schasinglulu }; 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* prototype */ 25*91f16700Schasinglulu uint32_t bcm_dmu_block_enable(struct DmuBlockEnable dbe); 26*91f16700Schasinglulu uint32_t bcm_dmu_block_disable(struct DmuBlockEnable dbe); 27*91f16700Schasinglulu uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel); 28*91f16700Schasinglulu uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num); 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define PLL_FREQ_BYPASS 0x0 31*91f16700Schasinglulu #define PLL_FREQ_FULL 0x1 32*91f16700Schasinglulu #define PLL_FREQ_HALF 0x2 33*91f16700Schasinglulu #define PLL_FREQ_QRTR 0x3 34*91f16700Schasinglulu 35*91f16700Schasinglulu #endif 36