1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef TZC400_H 8*91f16700Schasinglulu #define TZC400_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <drivers/arm/tzc_common.h> 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define BUILD_CONFIG_OFF U(0x000) 14*91f16700Schasinglulu #define GATE_KEEPER_OFF U(0x008) 15*91f16700Schasinglulu #define SPECULATION_CTRL_OFF U(0x00c) 16*91f16700Schasinglulu #define INT_STATUS U(0x010) 17*91f16700Schasinglulu #define INT_CLEAR U(0x014) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define FAIL_ADDRESS_LOW_OFF U(0x020) 20*91f16700Schasinglulu #define FAIL_ADDRESS_HIGH_OFF U(0x024) 21*91f16700Schasinglulu #define FAIL_CONTROL_OFF U(0x028) 22*91f16700Schasinglulu #define FAIL_ID U(0x02c) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* ID registers not common across different varieties of TZC */ 25*91f16700Schasinglulu #define PID5 U(0xFD4) 26*91f16700Schasinglulu #define PID6 U(0xFD8) 27*91f16700Schasinglulu #define PID7 U(0xFDC) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define BUILD_CONFIG_NF_SHIFT 24 30*91f16700Schasinglulu #define BUILD_CONFIG_NF_MASK U(0x3) 31*91f16700Schasinglulu #define BUILD_CONFIG_AW_SHIFT 8 32*91f16700Schasinglulu #define BUILD_CONFIG_AW_MASK U(0x3f) 33*91f16700Schasinglulu #define BUILD_CONFIG_NR_SHIFT 0 34*91f16700Schasinglulu #define BUILD_CONFIG_NR_MASK U(0x1f) 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* 37*91f16700Schasinglulu * Number of gate keepers is implementation defined. But we know the max for 38*91f16700Schasinglulu * this device is 4. Get implementation details from BUILD_CONFIG. 39*91f16700Schasinglulu */ 40*91f16700Schasinglulu #define GATE_KEEPER_OS_SHIFT 16 41*91f16700Schasinglulu #define GATE_KEEPER_OS_MASK U(0xf) 42*91f16700Schasinglulu #define GATE_KEEPER_OR_SHIFT 0 43*91f16700Schasinglulu #define GATE_KEEPER_OR_MASK U(0xf) 44*91f16700Schasinglulu #define GATE_KEEPER_FILTER_MASK U(0x1) 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* Speculation is enabled by default. */ 47*91f16700Schasinglulu #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1) 48*91f16700Schasinglulu #define SPECULATION_CTRL_READ_DISABLE BIT_32(0) 49*91f16700Schasinglulu 50*91f16700Schasinglulu /* Max number of filters allowed is 4. */ 51*91f16700Schasinglulu #define INT_STATUS_OVERLAP_SHIFT 16 52*91f16700Schasinglulu #define INT_STATUS_OVERLAP_MASK U(0xf) 53*91f16700Schasinglulu #define INT_STATUS_OVERRUN_SHIFT 8 54*91f16700Schasinglulu #define INT_STATUS_OVERRUN_MASK U(0xf) 55*91f16700Schasinglulu #define INT_STATUS_STATUS_SHIFT 0 56*91f16700Schasinglulu #define INT_STATUS_STATUS_MASK U(0xf) 57*91f16700Schasinglulu 58*91f16700Schasinglulu #define INT_CLEAR_CLEAR_SHIFT 0 59*91f16700Schasinglulu #define INT_CLEAR_CLEAR_MASK U(0xf) 60*91f16700Schasinglulu 61*91f16700Schasinglulu #define FAIL_CONTROL_DIR_SHIFT 24 62*91f16700Schasinglulu #define FAIL_CONTROL_DIR_READ U(0) 63*91f16700Schasinglulu #define FAIL_CONTROL_DIR_WRITE U(1) 64*91f16700Schasinglulu #define FAIL_CONTROL_NS_SHIFT 21 65*91f16700Schasinglulu #define FAIL_CONTROL_NS_SECURE U(0) 66*91f16700Schasinglulu #define FAIL_CONTROL_NS_NONSECURE U(1) 67*91f16700Schasinglulu #define FAIL_CONTROL_PRIV_SHIFT 20 68*91f16700Schasinglulu #define FAIL_CONTROL_PRIV_UNPRIV U(0) 69*91f16700Schasinglulu #define FAIL_CONTROL_PRIV_PRIV U(1) 70*91f16700Schasinglulu 71*91f16700Schasinglulu /* 72*91f16700Schasinglulu * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. 73*91f16700Schasinglulu * Platform should provide the value on initialisation. 74*91f16700Schasinglulu */ 75*91f16700Schasinglulu #define FAIL_ID_VNET_SHIFT 24 76*91f16700Schasinglulu #define FAIL_ID_VNET_MASK U(0xf) 77*91f16700Schasinglulu #define FAIL_ID_ID_SHIFT 0 78*91f16700Schasinglulu 79*91f16700Schasinglulu #define TZC_400_PERIPHERAL_ID U(0x460) 80*91f16700Schasinglulu 81*91f16700Schasinglulu /* Filter enable bits in a TZC */ 82*91f16700Schasinglulu #define TZC_400_REGION_ATTR_F_EN_MASK U(0xf) 83*91f16700Schasinglulu #define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x)) 84*91f16700Schasinglulu #define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* 87*91f16700Schasinglulu * All TZC region configuration registers are placed one after another. It 88*91f16700Schasinglulu * depicts size of block of registers for programming each region. 89*91f16700Schasinglulu */ 90*91f16700Schasinglulu #define TZC_400_REGION_SIZE U(0x20) 91*91f16700Schasinglulu #define TZC_400_ACTION_OFF U(0x4) 92*91f16700Schasinglulu 93*91f16700Schasinglulu #define FILTER_OFFSET U(0x10) 94*91f16700Schasinglulu 95*91f16700Schasinglulu #ifndef __ASSEMBLER__ 96*91f16700Schasinglulu 97*91f16700Schasinglulu #include <cdefs.h> 98*91f16700Schasinglulu #include <stdint.h> 99*91f16700Schasinglulu 100*91f16700Schasinglulu /******************************************************************************* 101*91f16700Schasinglulu * Function & variable prototypes 102*91f16700Schasinglulu ******************************************************************************/ 103*91f16700Schasinglulu void tzc400_init(uintptr_t base); 104*91f16700Schasinglulu void tzc400_configure_region0(unsigned int sec_attr, 105*91f16700Schasinglulu unsigned int ns_device_access); 106*91f16700Schasinglulu void tzc400_configure_region(unsigned int filters, 107*91f16700Schasinglulu unsigned int region, 108*91f16700Schasinglulu unsigned long long region_base, 109*91f16700Schasinglulu unsigned long long region_top, 110*91f16700Schasinglulu unsigned int sec_attr, 111*91f16700Schasinglulu unsigned int nsaid_permissions); 112*91f16700Schasinglulu void tzc400_update_filters(unsigned int region, unsigned int filters); 113*91f16700Schasinglulu void tzc400_set_action(unsigned int action); 114*91f16700Schasinglulu void tzc400_enable_filters(void); 115*91f16700Schasinglulu void tzc400_disable_filters(void); 116*91f16700Schasinglulu int tzc400_it_handler(void); 117*91f16700Schasinglulu 118*91f16700Schasinglulu static inline void tzc_init(uintptr_t base) 119*91f16700Schasinglulu { 120*91f16700Schasinglulu tzc400_init(base); 121*91f16700Schasinglulu } 122*91f16700Schasinglulu 123*91f16700Schasinglulu static inline void tzc_configure_region0( 124*91f16700Schasinglulu unsigned int sec_attr, 125*91f16700Schasinglulu unsigned int ns_device_access) 126*91f16700Schasinglulu { 127*91f16700Schasinglulu tzc400_configure_region0(sec_attr, ns_device_access); 128*91f16700Schasinglulu } 129*91f16700Schasinglulu 130*91f16700Schasinglulu static inline void tzc_configure_region( 131*91f16700Schasinglulu unsigned int filters, 132*91f16700Schasinglulu unsigned int region, 133*91f16700Schasinglulu unsigned long long region_base, 134*91f16700Schasinglulu unsigned long long region_top, 135*91f16700Schasinglulu unsigned int sec_attr, 136*91f16700Schasinglulu unsigned int ns_device_access) 137*91f16700Schasinglulu { 138*91f16700Schasinglulu tzc400_configure_region(filters, region, region_base, 139*91f16700Schasinglulu region_top, sec_attr, ns_device_access); 140*91f16700Schasinglulu } 141*91f16700Schasinglulu 142*91f16700Schasinglulu static inline void tzc_set_action(unsigned int action) 143*91f16700Schasinglulu { 144*91f16700Schasinglulu tzc400_set_action(action); 145*91f16700Schasinglulu } 146*91f16700Schasinglulu 147*91f16700Schasinglulu 148*91f16700Schasinglulu static inline void tzc_enable_filters(void) 149*91f16700Schasinglulu { 150*91f16700Schasinglulu tzc400_enable_filters(); 151*91f16700Schasinglulu } 152*91f16700Schasinglulu 153*91f16700Schasinglulu static inline void tzc_disable_filters(void) 154*91f16700Schasinglulu { 155*91f16700Schasinglulu tzc400_disable_filters(); 156*91f16700Schasinglulu } 157*91f16700Schasinglulu 158*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 159*91f16700Schasinglulu 160*91f16700Schasinglulu #endif /* TZC400_H */ 161