1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SMMU_V3_H 8*91f16700Schasinglulu #define SMMU_V3_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* SMMUv3 register offsets from device base */ 15*91f16700Schasinglulu #define SMMU_CR0 U(0x0020) 16*91f16700Schasinglulu #define SMMU_CR0ACK U(0x0024) 17*91f16700Schasinglulu #define SMMU_GBPA U(0x0044) 18*91f16700Schasinglulu #define SMMU_S_IDR1 U(0x8004) 19*91f16700Schasinglulu #define SMMU_S_INIT U(0x803c) 20*91f16700Schasinglulu #define SMMU_S_GBPA U(0x8044) 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* 23*91f16700Schasinglulu * TODO: SMMU_ROOT_PAGE_OFFSET is platform specific. 24*91f16700Schasinglulu * Currently defined as a command line model parameter. 25*91f16700Schasinglulu */ 26*91f16700Schasinglulu #if ENABLE_RME 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET) 29*91f16700Schasinglulu #define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000) 30*91f16700Schasinglulu #define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008) 31*91f16700Schasinglulu #define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020) 32*91f16700Schasinglulu #define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024) 33*91f16700Schasinglulu #define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028) 34*91f16700Schasinglulu #define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030) 35*91f16700Schasinglulu #define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038) 36*91f16700Schasinglulu #define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040) 37*91f16700Schasinglulu #define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050) 38*91f16700Schasinglulu #define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058) 39*91f16700Schasinglulu 40*91f16700Schasinglulu #endif /* ENABLE_RME */ 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* SMMU_CR0 and SMMU_CR0ACK register fields */ 43*91f16700Schasinglulu #define SMMU_CR0_SMMUEN (1UL << 0) 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* SMMU_GBPA register fields */ 46*91f16700Schasinglulu #define SMMU_GBPA_UPDATE (1UL << 31) 47*91f16700Schasinglulu #define SMMU_GBPA_ABORT (1UL << 20) 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* SMMU_S_IDR1 register fields */ 50*91f16700Schasinglulu #define SMMU_S_IDR1_SECURE_IMPL (1UL << 31) 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* SMMU_S_INIT register fields */ 53*91f16700Schasinglulu #define SMMU_S_INIT_INV_ALL (1UL << 0) 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* SMMU_S_GBPA register fields */ 56*91f16700Schasinglulu #define SMMU_S_GBPA_UPDATE (1UL << 31) 57*91f16700Schasinglulu #define SMMU_S_GBPA_ABORT (1UL << 20) 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* SMMU_ROOT_IDR0 register fields */ 60*91f16700Schasinglulu #define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0) 61*91f16700Schasinglulu 62*91f16700Schasinglulu /* SMMU_ROOT_CR0 register fields */ 63*91f16700Schasinglulu #define SMMU_ROOT_CR0_GPCEN (1UL << 1) 64*91f16700Schasinglulu #define SMMU_ROOT_CR0_ACCESSEN (1UL << 0) 65*91f16700Schasinglulu 66*91f16700Schasinglulu int smmuv3_init(uintptr_t smmu_base); 67*91f16700Schasinglulu int smmuv3_security_init(uintptr_t smmu_base); 68*91f16700Schasinglulu 69*91f16700Schasinglulu int smmuv3_ns_set_abort_all(uintptr_t smmu_base); 70*91f16700Schasinglulu 71*91f16700Schasinglulu #endif /* SMMU_V3_H */ 72