1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef GIC600_MULTICHIP_H 9*91f16700Schasinglulu #define GIC600_MULTICHIP_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* 14*91f16700Schasinglulu * GIC-600 microarchitecture supports coherent multichip environments containing 15*91f16700Schasinglulu * up to 16 chips. 16*91f16700Schasinglulu */ 17*91f16700Schasinglulu #define GIC600_MAX_MULTICHIP 16 18*91f16700Schasinglulu 19*91f16700Schasinglulu typedef struct multichip_spi_ids_desc { 20*91f16700Schasinglulu uintptr_t gicd_base; 21*91f16700Schasinglulu uint32_t spi_id_min; 22*91f16700Schasinglulu uint32_t spi_id_max; 23*91f16700Schasinglulu } multichip_spi_ids_desc_t; 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * GIC-600 multichip data structure describes platform specific attributes 27*91f16700Schasinglulu * related to GIC-600 multichip. Platform port is expected to define these 28*91f16700Schasinglulu * attributes to initialize the multichip related registers and create 29*91f16700Schasinglulu * successful connections between the GIC-600s in a multichip system. 30*91f16700Schasinglulu * 31*91f16700Schasinglulu * The 'rt_owner_base' field contains the base address of the GIC Distributor 32*91f16700Schasinglulu * which owns the routing table. 33*91f16700Schasinglulu * 34*91f16700Schasinglulu * The 'rt_owner' field contains the chip number which owns the routing table. 35*91f16700Schasinglulu * Chip number or chip_id starts from 0. 36*91f16700Schasinglulu * 37*91f16700Schasinglulu * The 'chip_count' field contains the total number of chips in a multichip 38*91f16700Schasinglulu * system. This should match the number of entries in 'chip_addrs' and 'spi_ids' 39*91f16700Schasinglulu * fields. 40*91f16700Schasinglulu * 41*91f16700Schasinglulu * The 'chip_addrs' field contains array of chip addresses. These addresses are 42*91f16700Schasinglulu * implementation specific values. 43*91f16700Schasinglulu * 44*91f16700Schasinglulu * The 'multichip_spi_ids_desc_t' field contains array of descriptors used to 45*91f16700Schasinglulu * provide minimum and maximum SPI interrupt ids that each chip owns and the 46*91f16700Schasinglulu * corresponding chip base address. Note that SPI interrupt ids can range from 47*91f16700Schasinglulu * 32 to 960 and it should be group of 32 (i.e., SPI minimum and (SPI maximum + 48*91f16700Schasinglulu * 1) should be a multiple of 32). If a chip doesn't own any SPI interrupts a 49*91f16700Schasinglulu * value of {0, 0, 0} should be passed. 50*91f16700Schasinglulu ******************************************************************************/ 51*91f16700Schasinglulu struct gic600_multichip_data { 52*91f16700Schasinglulu uintptr_t rt_owner_base; 53*91f16700Schasinglulu unsigned int rt_owner; 54*91f16700Schasinglulu unsigned int chip_count; 55*91f16700Schasinglulu uint64_t chip_addrs[GIC600_MAX_MULTICHIP]; 56*91f16700Schasinglulu multichip_spi_ids_desc_t spi_ids[GIC600_MAX_MULTICHIP]; 57*91f16700Schasinglulu }; 58*91f16700Schasinglulu 59*91f16700Schasinglulu uintptr_t gic600_multichip_gicd_base_for_spi(uint32_t spi_id); 60*91f16700Schasinglulu void gic600_multichip_init(struct gic600_multichip_data *multichip_data); 61*91f16700Schasinglulu bool gic600_multichip_is_initialized(void); 62*91f16700Schasinglulu 63*91f16700Schasinglulu #endif /* GIC600_MULTICHIP_H */ 64